UTOPIA16EVK/NOPB National Semiconductor, UTOPIA16EVK/NOPB Datasheet - Page 65

• Manufacturer Part Number: UTOPIA16EVK/NOPB
• Manufacturer: National Semiconductor

Specifications of UTOPIA16EVK/NOPB

• Lead Free Status / Rohs Status: Compliant

MTBQT1 0xC6
MTBQT0 0xC7
MTBQFL3
0xC8
MTBQT29
0xC9
MTBQFL1
0xCA
MTBQFL0
0xCB
MTBQE3
0xCC
MTBQT29
0xCD
MTBQE1 0xCE
MTBQE0 0xCF
18.0 Register Description
Type:
Software Lock: Yes
Reset Value:
The MTB Queue Threshold registers define the maximum size, in PDU cells, of each of the 31 queues. If all 31 queues are being
used, it is recommended that the threshold be left at the default of 4 cells. If less than 31 queues are in use, then the queue
threshold may be raised according to Section 9.1 SINGLE BRIDGE MTB CONFIGURATION.
18.65 MTB QUEUE FULL — 0xC8 to 0xCB MTBQFL3 to MTBQFL0
Type:
Software Lock: No
Reset Value:
The MTBQFL3, MTBQFL2, MTBQFL1 and MTBQFL0 registers show which queues are full.
18.66 MTB QUEUE EMPTY — 0xCC to 0xCF MTBQE3 to MTBQE0
Type:
Software Lock: No
Reset Value:
The MTBQE3, MTBQE2, MTBQE1 and MTBQE0 registers show which queues are empty.
18.67 MTB QUEUE FLUSH — 0xD0 to 0xD3 MTBQF3 to MTBQF0
• MTBQT30[7:0] Maximum number of PDU cells for queue 30.
• MTBQT29[7:0] Maximum number of PDU cells for queue 29.
• ...................
• MTBQT1[7:0] Maximum number of PDU cells for queue 1.
• MTBQT0[7:0] Maximum number of PDU cells for queue 0.
• MTBQFL3[7] MTBQFL3[7] bit indicates that the entire MTB is full. As memory resources are over assigned among the 31
• MTBQFL3–MTBQFL0 MTBQFL3[6] corresponds to queue 31 and MTBQFL0[0] corresponds to queue 0. When a bit is set,
• MTBQE3–MTBQE0 MTBQE3[6] corresponds to queue 31 and MTBQE0[0] corresponds to queue 0. When a bit is set, then
individual queues then the MTB may be full while some of the individual queues may not be full. When this bit is set, then the
entire queue is full and when clear, the queue is not full.
then the queue is full and when clear, the queue is not full.
the queue is empty and when clear, the queue is not empty.
MTBQFL3[7]
MTBQFL2[7]
MTBQFL1[7]
MTBQFL0[7]
MTBQT1[7]
MTBQT0[7]
MTBQE2[7]
MTBQE1[7]
MTBQE0[7]
Reserved
Read/Write
0x04
Read only
0x00
Read only
0xFF, except MTBQE3 = 0x7F
7
7
7
MTBQFL3[6]
MTBQFL2[6]
MTBQFL1[6]
MTBQFL0[6]
MTBQT1[6]
MTBQT0[6]
MTBQE3[6]
MTBQE2[6]
MTBQE1[6]
MTBQE0[6]
6
6
6
TABLE 84. MTBQT30–MTBQT0 (Continued)
MTBQFL3[5]
MTBQFL2[5]
MTBQFL1[5]
MTBQFL0[5]
MTBQT1[5]
MTBQT0[5]
MTBQE3[5]
MTBQE2[5]
MTBQE1[5]
MTBQE0[5]
(Continued)
TABLE 85. MTBQFL3–MTBQFL0
TABLE 86. MTBQE3–MTBQE0
5
5
5
MTBQFL3[4]
MTBQFL2[4]
MTBQFL1[4]
MTBQFL0[4]
MTBQT1[4]
MTBQT0[4]
MTBQE3[4]
MTBQE2[4]
MTBQE1[4]
MTBQE0[4]
65
4
4
4
MTBQFL3[3]
MTBQFL2[3]
MTBQFL1[3]
MTBQFL0[3]
MTBQT1[3]
MTBQT0[3]
MTBQE3[3]
MTBQE2[3]
MTBQE1[3]
MTBQE0[3]
3
3
3
MTBQFL3[2]
MTBQFL2[2]
MTBQFL1[2]
MTBQFL0[2]
MTBQT1[2]
MTBQT0[2]
MTBQE3[2]
MTBQE2[2]
MTBQE1[2]
MTBQE0[2]
2
2
2
MTBQFL3[1]
MTBQFL2[1]
MTBQFL1[1]
MTBQFL0[1]
MTBQT1[1]
MTBQT0[1]
MTBQE3[1]
MTBQE2[1]
MTBQE1[1]
MTBQE0[1]
1
1
1
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MTBQFL3[0]
MTBQFL2[0]
MTBQFL1[0]
MTBQFL0[0]
MTBQT1[0]
MTBQT0[0]
MTBQE3[0]
MTBQE2[0]
MTBQE1[0]
MTBQE0[0]
0
0
0