UTOPIA16EVK/NOPB National Semiconductor, UTOPIA16EVK/NOPB Datasheet - Page 79

• Manufacturer Part Number: UTOPIA16EVK/NOPB
• Manufacturer: National Semiconductor

Specifications of UTOPIA16EVK/NOPB

• Lead Free Status / Rohs Status: Compliant

t
t
t
t
t
t
t
t
t
t
t
t
DSR1
DRS2
RNM
LLH
LHL
SETUP
HOLD
RFCP
RFDC
RFCP
RFTT
JIT
Symbol
Symbol
Symbol
24.0 Electrical Characteristics
LVDS Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 14)
Timing Requirements for Input Clock
LVDS_TxClk, LVDS_ARefClk, LVDS_BRefClk
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 14)
Microprocessor Interface Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 14)
Note 13: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are meant to imply that the devices should
be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 14: Typical values are given for V
Note 15: Current into the device is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except V
V
Note 16: For the purpose of specifying deserializer P
of the incoming data stream (SYNCPATs). t
time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI−) conditions change from not receiving data to receiving
synchronization patterns (SYNCPATs). The time to lock to random data is dependent upon the incoming data.
Note 17: t
TL
/t
which are differential voltages.
TCP
RNM
Deserializer PLL Lock
Time from PWRDN (with
SYNCPAT)
Deserializer PLL Lock
Time from SYNCPAT
Deserializer Noise Margin
Low-to-High Transition
Time
High-to-Low Transition
Time
REFCLK Period
REFCLK Duty Cycle
Ratio of REFCLK to TCLK
REFCLK Transition Time
Input Jitter
is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur.
Parameter
Parameter
Parameter
CC
DSR1
= 3.3V and T
is the time required for the deserializer to indicate lock upon power-up or when the power-down mode. t
(Figure 28)
(Figure 29)
(Figure 30)
C
C
See Section 17.0
Microprocessor Interface
Operation
(Figure 27)
Jitter Frequency
Jitter Frequency
Jitter Frequency
L
L
= 15 pF (Figure 26)
= 15 pF (Figure 26)
LL
performance t
A
= 25˚C
Conditions
Conditions
Conditions
(Continued)
(Continued)
DSR1
<
<
<
250 kHz
250 kHz
250 kHz
and t
79
DSR2
are specified with the REFCLK running and stable, and specific conditions
LVDS_ADin[+,−],
LVDS_BDin[+.,−]
Pin/Freq.
Pin/Freq.
Outputs
Inputs
Pin/Freq.
19.2
Min
40
−5
Min
Min
400
Typ
50
Typ
Typ
Max
0.15
1.5
Max
60
15
Max
5
8
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30
12
6
6
OD
DSR2
, V
TH
is the
Units
Units
Units
and
ns
ns
UI
UI
UI
%
%
µs
µs
ps
ns
ns