UTOPIA16EVK/NOPB National Semiconductor, UTOPIA16EVK/NOPB Datasheet - Page 73

• Manufacturer Part Number: UTOPIA16EVK/NOPB
• Manufacturer: National Semiconductor

Specifications of UTOPIA16EVK/NOPB

• Lead Free Status / Rohs Status: Compliant

B8
C8
D8
C9
C11
C12
G9
B5
B6
C5
C6
A8
B9
D9
D12
E12
A5
D5
D6
L2
D13
F11
F10
F13
G11
G12
H11
G13
H12
F14
H13
H14
J13
J14
N13
N14
P14
L11
P13
M12
P12
K10
N12
P11
N11
M11
M10
J10
20.0 Package
Ball
PGND
PGND
PGND
PGNDA
PGNDA
PGNDA
PGNDA
PGNDB
PGNDB
PGNDB
PGNDB
PV
PV
PV
PV
PV
PV
PV
PV
Reset_n
Test_se
U_RxAddr[0]
U_RxAddr[1]
U_RxAddr[2]
U_RxAddr[3]
U_RxAddr[4]
U_RxCLAV [0]
U_RxCLAV [1]
U_RxCLAV [2]
U_RxCLAV [3]
U_RxCLAV [4]
U_RxCLAV [5]
U_RxCLAV [6]
U_RxCLAV [7]
U_RxData [0]
U_RxData [1]
U_RxData [2]
U_RxData [3]
U_RxData [4]
U_RxData [5]
U_RxData [6]
U_RxData [7]
U_RxData [8]
U_RxData [9]
U_RxData [10]
U_R xData [11]
U_RxData [12]
U_RxData [13]
DD
DD
DDA
DDA
DDA
DDB
DDB
DDB
Pin Name
(Continued)
TABLE 96. Pin Locations — BGA196 Package (Continued)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
Input LVTTL
Input LVTTL
BiDir LVTTL
BiDir LVTTL
BiDir LVTTL
BiDir LVTTL
BiDir LVTTL
BiDir LVTTL
Input LVTTL
Input LVTTL
Input LVTTL
Input LVTTL
Input LVTTL
Input LVTTL
Input LVTTL
BiDir LVTTL
BiDir LVTTL
BiDir LVTTL
BiDir LVTTL
BiDir LVTTL
BiDir LVTTL
BiDir LVTTL
BiDir LVTTL
BiDir LVTTL
BiDir LVTTL
BiDir LVTTL
BiDir LVTTL
BiDir LVTTL
BiDir LVTTL
Signal Type
GND for Transmit PLL
GND for Transmit PLL
GND for Transmit PLL
GND for PLL A
GND for PLL A
GND for PLL A
GND for PLL A
GND for PLL B
GND for PLL B
GND for PLL B
GND for PLL B
Transmit PLL V
Transmit PLL V
V
V
V
V
V
V
Chip Reset Control
Scan Enable
Address of MPHY Device Being Polled or Selected
Address of MPHY Device Being Polled or Selected
Address of MPHY Device Being Polled or Selected
Address of MPHY Device Being Polled or Selected
Address of MPHY Device Being Polled or Selected
Receive Cell Available — Normal/Extended PHY Port Control
Receive Cell Available — Normal/Extended PHY Port Control
Receive Cell Available — Normal/Extended PHY Port Control
Receive Cell Available — Normal/Extended PHY Port Control
Receive Cell Available — Extended PHY Port Control
Receive Cell Available — Extended PHY Port Control
Receive Cell Available — Extended PHY Port Control
Receive Cell Available — Extended PHY Port Control
Receive Data Bus, from the PHY Layer Device(s)
Receive Data Bus, from the PHY Layer Device(s)
Receive Data Bus, from the PHY Layer Device(s)
Receive Data Bus, from the PHY Layer Device(s)
Receive Data Bus, from the PHY Layer Device(s)
Receive Data Bus, from the PHY Layer Device(s)
Receive Data Bus, from the PHY Layer Device(s)
Receive Data Bus, from the PHY Layer Device(s)
Receive Data Bus, from the PHY Layer Device(s)
Receive Data Bus, from the PHY Layer Device(s)
Receive Data Bus, from the PHY Layer Device(s)
Receive Data Bus, from the PHY Layer Device(s)
Receive Data Bus, from the PHY Layer Device(s)
Receive Data Bus, from the PHY Layer Device(s)
DD
DD
DD
DD
DD
DD
73
for PLL A
for PLL A
for PLL A
for PLL B
for PLL B
for PLL B
DD
DD
Description
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