UTOPIA16EVK/NOPB National Semiconductor, UTOPIA16EVK/NOPB Datasheet - Page 47

• Manufacturer Part Number: UTOPIA16EVK/NOPB
• Manufacturer: National Semiconductor

Specifications of UTOPIA16EVK/NOPB

• Lead Free Status / Rohs Status: Compliant

18.0 Register Description
18.9 TRANSMIT LINK LABEL — 0x09 TXLL
Type:
Software Lock: No
Reset Value:
The Transmit Link Label register defines the contents of the Link Trace Label byte transmitted in TC6.
18.10 ECC TRANSMIT BUFFER AND RECEIVE LVDS ALARMS — 0x0A ETXRXA
Type:
Software Lock: No
Reset Value:
This register contains the status of the ECC transmit buffer and the LOCK signals from the two LVDS receive ports. When set the
LLOSA, LLOSB and LLOSC bits will raise an interrupt if the corresponding interrupt enable bit is set.
• ECCA ECC active on Port A bit. When set, this indicates to the ECC transmit section that the ETXBR bit (Section 18.10 ECC
• ECCB ECC active on Port B bit. When set, this indicates to the ECC transmit section that the ETXBR bit (Section 18.10 ECC
• ECCB and ECCA Note that when both these bits are clear, then the ECC transmitter and both receivers are inactive. The
• ECCB and ECCA Note that when both these bits are set, this indicates to the ECC transmit section that the ETXBR bit will
• ABSC A/B Switch completed. When switching active traffic receive port this bit can be polled by the processor to determine
• LBA Local receive port A or B control. When this bit is set, then Receive Port B is Active and Port A is Standby. When clear,
• FTXSCR Force Transmit Scrambler Sequence. When set this forces the transmission of the scrambler sequence which is
• TXLL[7:0] Transmitted Link Trace Label byte contents.
• LLOSA Local Loss Of Signal on receive Port A. When set this will also clear all the bits in the Receive Port A Remote Alarms
• LLOSB Local Loss Of Signal on receive Port B. When set this will also clear all the bits in the Receive Port B Remote Alarms
• LLOSC Local Loss Of Signal Change. When set this indicates that there has been a change of value for either LLOSA or
TRANSMIT BUFFER AND RECEIVE LVDS ALARMS — 0x0A ETXRXA) will be set only when the far end ECC receiver
connected to Port A indicates via the ECC signalling (received ESSA or ESSB signal, as selected by bit RAESS of register
RACTL) over Port A that the message has been received successfully. When clear the ECC signalling over Port A will be
ignored as the ECC Port A receiver is disabled and the ERABF bit will be held clear. See Section 16.0 Embedded
Communication Channel Operation.
TRANSMIT BUFFER AND RECEIVE LVDS ALARMS — 0x0A ETXRXA) will be set only when the far end ECC receiver
connected to Port B indicates via the ECC signalling (received ESSA or ESSB signal, as selected by bit RBESS of register
RBCTL) over Port B that the message has been received successfully. When clear the ECC signalling over Port B will be
ignored as the ECC Port B receiver is disabled and the ERBBF bit will be held clear. See Section 16.0 Embedded
Communication Channel Operation.
ETXBR, ETXSD, ERABF and ERBBF bits will be held clear, the ECC signalling is ignored and no messages are transmitted
or received. See Section 16.0 Embedded Communication Channel Operation.
only be set when both far end ECC receivers indicate that the transmitted message has been received successfully (received
ESS signals). See Section 16.0 Embedded Communication Channel Operation.
when the switch has been completed successfully. A change of the LBA bit will clear this bit. The ABSC bit should then be
polled by the processor. The ABSC bit is set by the hardware when the active port switching is completed. This bit relates to
the LBA active traffic switching bit and is not related to the ECC port switching bit ECCA and ECCB. See Section 13.0
Switching Receive Ports.
then Port A is Active and Port B is Standby. This bit defines the active traffic port and does not affect which ECC channel is
active as defined by the ECCA and ECCB bits above. See Section 13.0 Switching Receive Ports.
used to lock the descrambler.
register.
register.
LLOSB.
Reserved
TXLL[7]
7
7
Read/Write
0x00
Bits[3:1] Read only/Clear on Read
Bit[0] Read only
0x01
Reserved
TXLL[6]
6
6
Reserved
TXLL[5]
5
5
(Continued)
Reserved
TABLE 30. ETXRXA
TXLL[4]
TABLE 29. TXLL
4
4
47
TXLL[3]
LLOSC
3
3
TXLL[2]
LLOSA
2
2
TXLL[1]
LLOSB
1
1
TXLL[0]
ETXBR
0
0
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