UTOPIA16EVK/NOPB National Semiconductor, UTOPIA16EVK/NOPB Datasheet - Page 68

• Manufacturer Part Number: UTOPIA16EVK/NOPB
• Manufacturer: National Semiconductor

Specifications of UTOPIA16EVK/NOPB

• Lead Free Status / Rohs Status: Compliant

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ALFLT3 0xF7
ALFLT2 0xF8
ALFLT1 0xF9
ALFLT0 0xFA
18.0 Register Description
18.73 UTOPIA AND ATM INTERRUPT ENABLES — 0xE2 UAIE
Type:
Software Lock: No
Reset Value:
This register contains the interrupt enables for the alarms in the UAA register. Set = interrupt enabled and Clear = interrupt
disabled.
18.74 ATM LOOPBACK CELL FILTER — 0xF7 to 0xFA ALFLT3 to AFLT0
Type:
Software Lock: No
Reset Value:
The ALBCF3, ALBCF2, ALBCF1 and ALBCF0 registers (See Section 7.20) define the cell header bytes filter for detecting ATM
loopback cells. Incoming ATM cells are compared against the loopback cell header format defined in the ALBCF3–ALBCF0
registers to determine if they are loopback cells. The filter defined in the ALFLT3–ALFLT0 registers is used to determine which
bits of the four byte cell header are compared. If a bit is set then that bit in the incoming cell header is compared against the
corresponding bit in the ALBCF3–ALBCF0 registers. Only those bits which are set in the ALFLT3–ALFLT0 registers are compared
to determine if a cell is a loopback cell.
19.0 Test Features
19.1 TEST STRUCTURES
The DS92UT16 device has the following test structures in
place.
As shown, the device has a AP controller which was gener-
ated using the LOGICVISION tool suite. This AP controller is
• FIBOV Set = FIB queue attempted to overflow (Equivalent functionality as the MTBQOV3–0 register bits).
• MTBSOV MTB Soft Overflow Alarm bit. Set = One or more of the bits in the MTBQOV3–MTBQOV0 registers are set. Clear
• MTBHOV MTB Hard Overflow Alarm bit. Set = MTB queue has attempted to overflow. This is a hard overflow as the overall
• ALBCF3[7:0] Loopback Cell header byte H1 filter.
• ALBCF2[7:0] Loopback Cell header byte H2 filter.
• ALBCF1[7:0] Loopback Cell header byte H3 filter.
• ALBCF0[7:0] Loopback Cell header byte H4 filter.
• Internal SCAN (manufacturing test only)
• RAM BIST (manufacturing test only)
• Boundary SCAN
= The MTBQOV3–MTBQOV0 registers are clear.
MTB has attempted to fill beyond it’s hard limit of 159 cells.
PDULIE
ALFLT3[7]
ALFLT2[7]
ALFLT1[7]
ALFLT0[7]
7
Read/Write
0x00
Read/Write
0xFF
7
CTFRIE
6
ALFLT3[6]
ALFLT2[6]
ALFLT1[6]
ALFLT0[6]
6
D2ULBCIE
5
ALFLT3[5]
ALFLT2[5]
ALFLT1[5]
ALFLT0[5]
(Continued)
5
TABLE 94. ALFLT3–ALFLT0
U2DLBCIE
TABLE 93. UAIE
4
ALFLT3[4]
ALFLT2[4]
ALFLT1[4]
ALFLT0[4]
68
4
UPRTYIE
used to configure the device for scan testing, RAM BIST and
Boundary Scan. The Instruction Register is shown in Figure
23. Bits 12–18 are not used. A more detailed description of
the operation of the TAP controller can be found in the
LOGICVISION document: Adding Logic Test — A Hardware
Reference July 2000. (NOTE: The Internal SCAN and RAM
BIST functions are not user accessible. Therefore, the de-
vice user should never assert the Test_se pin.)
3
ALFLT3[3]
ALFLT2[3]
ALFLT1[3]
ALFLT0[3]
3
FIBOVIE
2
ALFLT3[2]
ALFLT2[2]
ALFLT1[2]
ALFLT0[2]
MTBSOVAIE
2
1
ALFLT3[1]
ALFLT2[1]
ALFLT1[1]
ALFLT0[1]
MTBHOVIE
1
0
ALFLT3[0]
ALFLT2[0]
ALFLT1[0]
ALFLT0[0]
0