MT47H32M16BN-25:D Micron Technology Inc, MT47H32M16BN-25:D Datasheet - Page 66

• Manufacturer Part Number: MT47H32M16BN-25:D
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H32M16BN-25:D

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 400ps
• Maximum Clock Rate: 800MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 295mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

PDF: 09005aef82f1e6e2
Rev. M 9/08 EN
2.
3.
4. Although the total setup time might be negative for slow slew rates (a valid input signal
5. For slew rates between the values listed in this table, the derating values may be ob-
6. These values are typically not subject to production test. They are verified by design and
7. Single-ended DQS requires special derating. The values in Table 32 (page 68) are the
t
crossing of Vref(DC) and the first crossing of Vih(AC) MIN.
falling signal is defined as the slew rate between the last crossing of Vref(DC) and the
first crossing of Vil(AC) MAX. If the actual signal is always earlier than the nominal slew
rate line between the shaded “Vref(DC) to AC region,” use the nominal slew rate for
the derating value (see Figure 30 (page 70)). If the actual signal is later than the nomi-
nal slew rate line anywhere between the shaded “Vref(DC) to AC region,” the slew rate
of a tangent line to the actual signal from the AC level to DC level is used for the derat-
ing value (see Figure 31 (page 70)).
t
crossing of Vil(DC) MAX and the first crossing of Vref(DC).
falling signal is defined as the slew rate between the last crossing of Vih(DC) MIN and
the first crossing of Vref(DC). If the actual signal is always later than the nominal slew
rate line between the shaded “DC level to Vref(DC) region,” use the nominal slew rate
for the derating value (see Figure 32 (page 71)). If the actual signal is earlier than the
nominal slew rate line anywhere between shaded “DC to Vref(DC) region,” the slew
rate of a tangent line to the actual signal from the DC level to Vref(DC) level is used for
the derating value (see Figure 33 (page 71)).
will not have reached Vih[AC]/Vil[AC] at the time of the rising clock transition), a valid
input signal is still required to complete the transition and reach Vih(AC)/Vil(AC).
tained by linear interpolation.
characterization.
DQS single-ended slew rate derating with DQS referenced at Vref and DQ referenced at
the logic levels
to the AC/DC trip points to DQ referenced to Vref is listed in Table 34 (page 69) and
Table 35 (page 69). Table 34 (page 69) provides the Vref-based fully derated values
for the DQ (
fully derated values for the DQ (
DS nominal slew rate for a rising signal is defined as the slew rate between the last
DH nominal slew rate for a rising signal is defined as the slew rate between the last
t
DS
a
t
DS
and
b
and
t
DH
t
a
DH
) for DDR2-533. Table 35 (page 69) provides the Vref-based
66
b
. Converting the derated base values from DQ referenced
t
DS
a
Micron Technology, Inc. reserves the right to change products or specifications without notice.
and
512Mb: x4, x8, x16 DDR2 SDRAM
t
DH
a
) for DDR2-400.
Input Slew Rate Derating
t
t
DS nominal slew rate for a
DH nominal slew rate for a
© 2004 Micron Technology, Inc. All rights reserved.