MT47H32M16BN-25:D Micron Technology Inc, MT47H32M16BN-25:D Datasheet - Page 76

• Manufacturer Part Number: MT47H32M16BN-25:D
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H32M16BN-25:D

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 400ps
• Maximum Clock Rate: 800MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 295mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

PDF: 09005aef82f1e6e2
Rev. M 9/08 EN
10. A WRITE command may be applied after the completion of the READ burst.
4. The following states must not be interrupted by a command issued to the same bank.
5. The following states must not be interrupted by any executable command (DESELECT or
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle and bursts are not in progress.
8. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
9. May or may not be bank-specific; if multiple banks are to be precharged, each must be
Issue DESELECT or NOP commands, or allowable commands to the other bank, on any
clock edge occurring during these states. Allowable commands to the other bank are
determined by its current state and this table, and according to Table 38 (page 77).
NOP commands must be applied on each positive clock edge during these states):
auto precharge enabled and READs or WRITEs with auto precharge disabled.
in a valid state for precharging.
Precharge:
Read with auto
precharge
enabled:
Row activate:
Write with auto
precharge
enabled:
Refresh:
Accessing
mode
register:
Precharge all: Starts with registration of a PRECHARGE ALL command and ends
Starts with registration of a REFRESH command and ends when
met. After
state.
Starts with registration of the LOAD MODE command and ends when
t
the all banks idle state.
when
MRD has been met. After
Starts with registration of a PRECHARGE command and ends when
t
Starts with registration of a READ command with auto precharge
enabled and ends when
bank will be in the idle state.
Starts with registration of an ACTIVATE command and ends when
t
state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when
bank will be in the idle state.
RP is met. After
RCD is met. After
t
RP is met. After
76
t
RFC is met, the DDR2 SDRAM will be in the all banks idle
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RP is met, the bank will be in the idle state.
t
RCD is met, the bank will be in the row active
t
512Mb: x4, x8, x16 DDR2 SDRAM
RP is met, all banks will be in the idle state.
t
MRD is met, the DDR2 SDRAM will be in
t
t
RP has been met. After
RP has been met. After
© 2004 Micron Technology, Inc. All rights reserved.
t
t
RP is met, the
RP is met, the
Commands
t
RFC is