MT47H64M16HR-3 IT:HTR Micron Technology Inc, MT47H64M16HR-3 IT:HTR Datasheet - Page 119

• Manufacturer Part Number: MT47H64M16HR-3 IT:HTR
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H64M16HR-3 IT:HTR

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Figure 68: Self Refresh
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. W 7/11 EN
DQS#, DQS
Command
Address
ODT 6
CKE 1
CK#
CK 1
DM
DQ
t AOFD/ t AOFPD 6
NOP
T0
t CH
t RP 8
Notes:
Enter self refresh
mode (synchronous)
t CL
REF
10. Upon exiting SELF REFRESH, ODT must remain LOW until
T1
1. Clock must be stable and meeting
2. Self refresh exit is asynchronous; however,
3. CKE must stay HIGH until
4. NOP or DESELECT commands are required prior to exiting self refresh until state Tc0,
5.
6. ODT must be disabled and R
7.
8. Device must be in the all banks idle state prior to entering self refresh mode.
9. After self refresh has been entered,
refresh mode and at least 1 ×
ing clock edge where CKE HIGH satisfies
may go back LOW after
which allows any nonREAD command.
t
tering self refresh at state T1.
t
Td0.
fresh.
XSNR is required before any nonREAD command can be applied.
XSRD (200 cycles of CK) is required before a READ command can be applied at state
t CK 1
T2
t CKE (MIN) 9
Ta0
t
t CK 1
XSNR is satisfied.
119
t
Exit self refresh
mode (asynchronous)
XSRD is met; however, if self refresh is being re-entered, CKE
TT
t
Ta1
CK prior to exiting self refresh mode.
off (
t
t
CK specifications at least 1 ×
AOFD and
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
CKE (MIN) must be satisfied prior to exiting self re-
t ISXR 2
NOP 4
t
ISXR.
Ta2
t
XSNR and
1Gb: x4, x8, x16 DDR2 SDRAM
t CKE 3
t
AOFPD have been satisfied) prior to en-
t XSNR 2, 5, 10
NOP 4
Tb0
t
XSRD timing starts at the first ris-
Indicates a break in
time scale
t XSRD 2, 7
t
XSRD is satisfied.
‹ 2007 Micron Technology, Inc. All rights reserved.
Valid 5
Valid
t
CK after entering self
Tc0
SELF REFRESH
Don’t Care
Valid 7
Valid 5
Td0
W ,+
W ,+