MT47H64M16HR-3 IT:HTR Micron Technology Inc, MT47H64M16HR-3 IT:HTR Datasheet - Page 82
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MT47H64M16HR-3 IT:HTR
Manufacturer Part Number
MT47H64M16HR-3 IT:HTR
Description
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Specifications of MT47H64M16HR-3 IT:HTR
Organization
64Mx16
Density
1Gb
Address Bus
16b
Access Time (max)
450ps
Maximum Clock Rate
667MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
135mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant
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Write Recovery
Power-Down Mode
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. W 7/11 EN
Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 35 (page 80).
The WR register is used by the DDR2 SDRAM during WRITE with auto precharge opera-
tion. During WRITE with auto precharge operation, the DDR2 SDRAM delays the inter-
nal auto precharge operation by WR clocks (programmed in bits M9–M11) from the last
data burst. An example of WRITE with auto precharge is shown in Figure 64 (page 114).
WR values of 2, 3, 4, 5, 6, 7, or 8 clocks may be used for programming bits M9–M11. The
user is required to program the value of WR, which is calculated by dividing
nanoseconds) by
integer; WR (cycles) =
known operation or incompatibility with future versions may result.
Active power-down (PD) mode is defined by bit M12, as shown in Figure 35. PD mode
enables the user to determine the active power-down mode, which determines per-
formance versus power savings. PD mode bit M12 does not apply to precharge PD
mode.
When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled.
The
be enabled and running during this mode.
When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is en-
abled. The
be enabled but “frozen” during active PD mode because the exit-to-READ command
timing is relaxed. The power difference expected between I
power mode is defined in the DDR2 I
t
XARD parameter is used for fast-exit active PD exit timing. The DLL is expected to
t
XARDS parameter is used for slow-exit active PD exit timing. The DLL can
t
CK (in nanoseconds) and rounding up a noninteger value to the next
t
WR (ns)/
82
t
CK (ns). Reserved states should not be used as an un-
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Specifications and Conditions table.
1Gb: x4, x8, x16 DDR2 SDRAM
DD3P
Mode Register (MR)
2007 Micron Technology, Inc. All rights reserved.
normal and I
t
WR (in
DD3P
low-
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