MT47H64M16HR-3 IT:HTR Micron Technology Inc, MT47H64M16HR-3 IT:HTR Datasheet - Page 27
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MT47H64M16HR-3 IT:HTR
Manufacturer Part Number
MT47H64M16HR-3 IT:HTR
Description
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Specifications of MT47H64M16HR-3 IT:HTR
Organization
64Mx16
Density
1Gb
Address Bus
16b
Access Time (max)
450ps
Maximum Clock Rate
667MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
135mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant
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I
Table 9: I
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. W 7/11 EN
Timing patterns for 8-bank x4/x8 devices
Timing patterns for 8-bank x16 devices
DD7
Speed
Grade
-187E
-187E
-37E
-25E
-37E
-25E
-5E
-3E
-25
-5E
-3E
-25
-3
-3
Conditions
DD7
I
A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
D
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D A4 RA4 D D D D A5 RA5 D D D D A6 RA6 D
D D D A7 RA7 D D D D
DD7
Timing Patterns (8-Bank Interleave READ Operation)
Timing Patterns
Notes:
The detailed timings are shown below for I
Table 8 (page 26) conflict with pattern requirements of Table 9, then Table 9 require-
ments take precedence.
1. A = active; RA = read auto precharge; D = deselect.
2. All banks are being interleaved at
3. Control and address bus inputs are stable during deselects.
27
Electrical Specifications – I
t
RC (I
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DD
DD7
) without violating
. Where general I
1Gb: x4, x8, x16 DDR2 SDRAM
2007 Micron Technology, Inc. All rights reserved.
t
DD
RRD (I
parameters in
DD
DD
) using a BL = 4.
Parameters
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