SL72P8M64M8M-A05AYU STEC, SL72P8M64M8M-A05AYU Datasheet - Page 10

• Manufacturer Part Number: SL72P8M64M8M-A05AYU
• Manufacturer: STEC

Specifications of SL72P8M64M8M-A05AYU

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Access Time (max): 600ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.17A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

SL72P8M64M8M-A05AY(W)U
INPUT ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
Note: Values shown at DRAM inputs. For values at Register and PLL inputs, refer to the tables at the end of the document.
Input DC Logic Levels
Input AC Logic Levels
Differential Input Logic Levels
All voltages referenced to VSS.
Notes:
All voltages referenced to VSS.
All voltages referenced to VSS.
Symbol
VIN(DC)
VID(DC)
VID(AC)
VIX(AC)
VMP(DC)
1. VIN(DC) specifies the allowable DC execution of each
2. VID(DC) specifies the input differential voltage | VTR -
3. VID(AC) specifies the input differential voltage | VTR - VCP
input of differential pair such as CK, /CK, DQS, and /DQS.
VCP | required for switching, where VTR is the true input
(such as CK, DQS) level and VCP is the complementary
input (such as /CK, /DQS). The minimum value is equal
to VIH(DC) - VIL(DC).
| required for switching, where VTR is the true input (such
as CK, DQS, LDQS, UDQS, RDQS) level and VCP is the
complementary input (such as /CK, /DQS). The minimum
value is equal to VIH(AC) -VIL(AC).
Parameter
DC input signal voltage
DC differential input voltage
AC differential input voltage
AC differential cross-point voltage
Input midpoint voltage
Symbol
VIH(DC)
VIL(DC)
Symbol
VIH(AC)
VIL(AC)
Parameter
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Parameter
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
0.50 x VDDQ - 175 0.50 x VDDQ + 175
Document Part Number 61000-03657-105 November 2007 Page 10
-300
Min
250
500
850
VREF + 125
VREF + 250
4. The typical value of VIX(AC) is expected to be about 0.5 x
5. VMP(DC) specifies the input differential common mode
-300
Min
Min
-
VDDQ of the transmitting device and VIX(AC) is expected
to track variations in VDDQ. VIX(AC) indicates the voltage
at which differential input signals must cross.
voltage (VTR + VCP)/2 where VTR is the true input (CK,
DQS) level and VCP is the complementary input (/CK, /
DQS). VMP(DC) is expected to be approximately 0.5 x
VDDQ.
VDDQ + 300
VREF - 125
VREF - 250
VDDQ + 300
VDDQ + 600
VDDQ + 600
Max
Max
Max
950
-
240-PIN RDIMM
Units
Units
mV
mV
mV
mV
Units
mV
mV
mV
mV
mV
Notes
1
2
3
4
5