SL72P8M64M8M-A05AYU STEC, SL72P8M64M8M-A05AYU Datasheet - Page 6

• Manufacturer Part Number: SL72P8M64M8M-A05AYU
• Manufacturer: STEC

Specifications of SL72P8M64M8M-A05AYU

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Access Time (max): 600ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.17A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

SL72P8M64M8M-A05AY(W)U
SERIAL PRESENCE DETECT INFORMATION
Serial PD Interface Protocol: I
Byte Description
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
0
1
2
3
4
5
6
7
8
9
Number of SPD Bytes Used by STEC
Total Number of Bytes in SPD Device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
DIMM Height and Module Ranks
Module Data Width
Reserved
Module Voltage Interface Levels
SDRAM Cycle Time, tCK (CAS Latency= 5)
SDRAM Access from Clock,tAC (CAS Latency = 5)
Module Configuration Type
Refresh Rate/Type
SDRAM Device Width (Primary SDRAM)
Error-checking SDRAM Data Width
Reserved
Burst Lengths Supported
Number of Banks on SDRAM Device
CAS Latencies Supported
Reserved
DDR2 DIMM Type
SDRAM Module Attributes
SDRAM Device Attributes: General
SDRAM Cycle Time, tCK, (CAS Latency= 4)
SDRAM Access from CK, tAC, (CAS Latency = 4)
SDRAM Cycle Time, tCK, (CAS Latency = 3)
SDRAM Access from CK, tAC, (CAS Latency = 3)
Minimum Row Precharge Time, tRP
Minimum Row Active to Row Active, tRRD
Minimum /RAS to /CAS Delay, tRCD
Minimum /RAS Pulse Width, tRAS
Module Rank Density
Address and Command Setup Time, tIS
Address and Command Hold Time, tIH
Data/ Data Mask Input Setup Time, tDS
Data/ Data Mask Input Hold Time, tDH
Write Recovery Time, tWR
Write to Read CMD Delay, tWTR
Read to Precharge CMD Delay, tRTP
Mem Analysis Probe
Extension for bytes 41 and 42
Min Active Auto Refresh Time, tRC
Min. Auto Refresh to Active/ Auto Refresh Command Period, tRFC
SDRAM Device Max Cycle Time, tCKMAX
SDRAM Device Max DQS-DQ Skew Time, tDQSQ
2
C; Current sink capability of SDA driver <=3mA; Maximum clock frequency: 100 KHz
Document Part Number 61000-03657-105 November 2007 Page 6
(Serial Presence Detect Information continued on next page)
Supports weak driver
Non-parity addr/cmd,
30mm, planar, 1 rank
Regular RDIMM
SDRAM DDR2
7.81μs/SELF
0.0ns/0.0ns
SSTL 1.8V
Undefined
Undefined
Undefined
Undefined
Undefined
ECC data
±0.6ns
±0.6ns
±0.6ns
512MB
0.35ns
0.47ns
0.15ns
0.27ns
0.35ns
3, 4, 5
105ns
Entry
5.0ns
5.0ns
5.0ns
7.5ns
7.5ns
15ns
15ns
40ns
15ns
10ns
55ns
128
256
4, 8
8ns
14
10
72
x8
x8
4
240-PIN RDIMM
Hex Value
0A
0C
80
08
08
0E
60
48
00
05
50
60
02
82
08
08
00
04
38
00
01
00
01
50
60
50
60
3C
1E
3C
28
80
35
47
15
27
3C
28
1E
00
00
37
69
80
23