SL72P8M64M8M-A05AYU STEC, SL72P8M64M8M-A05AYU Datasheet - Page 16

• Manufacturer Part Number: SL72P8M64M8M-A05AYU
• Manufacturer: STEC

Specifications of SL72P8M64M8M-A05AYU

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Access Time (max): 600ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.17A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

SL72P8M64M8M-A05AY(W)U
NOTES
21. READS AND WRITES WITH AUTO PRECHARGE are
22. VIL/VIH DDR2 overshoot/undershoot. REFER TO the
23. tDAL = (nWR) + (tRP/tCK): For each of the terms above, if
24. The minimum READ to internal PRECHARGE time. This
25. Operating frequency is only allowed to change during self
26. ODT turn-on time tAON (MIN) is when the device leaves
27. ODT turn-off time tAOF (MIN) is when the device starts to
28. This parameter has a two clock minimum requirement at
allowed to be issued before tRAS (MIN) is satisfied since
tRAS lockout feature is supported in DDR2 SDRAM
devices.
256Mb, 512Mb, or 1Gb DDR2 SDRAM data sheet for more
detail.
not already an integer, round to the next highest integer.
tCK refers to the application clock period; nWR refers to
the tWR parameter stored in the MR[11,10,9]. Example:
For -53E at tCK = 3.75 ns with tWR programmed to four
clocks. tDAL = 4 + (15 ns/3.75 ns) clocks = 4 +(4) clocks
= 8 clocks.
parameter is only applicable when tRTP/(2*tCK) > 1. If
tRTP/(2*tCK) <= 1, then equation AL + BL/2 applies.
Notwithstanding, tRAS (MIN) has to be satisfied as well.
The DDR2 SDRAM device will automatically delay the
internal PRECHARGE command until tRAS (MIN) has
been satisfied.
refresh mode, precharge power-down mode, and system
reset condition.
high impedance and ODT resistance begins to turn on.
ODT turn-on time tAON (MAX) is when the ODT resistance
is fully on. Both are measured from tAOND.
turn off ODT resistance. ODT turn off time tAOF (MAX) is
when the bus is in high impedance. Both are measured
from tAOFD.
any tCK.
(continued)
Document Part Number 61000-03657-105 November 2007 Page 16
37. When DQS is used single-ended, the minimum limit is
29. tDELAY is calculated from tIS + tCK + tIH so that CKE
30. tISXR is equal to tIS and is used for CKE setup time during
31. No more than 4 bank ACTIVE commands may be issued
32. tRPA timing applies when the PRECHARGE(ALL)
33. Value is minimum pulse width, not the number of clock
34. Applicable to Read cycles only. Write cycles generally
35. tCKE (MIN) of 3 clocks means CKE must be registered
36. This parameter is not referenced to a specific voltage
registration LOW is guaranteed prior to CK, /CK being
removed in a system RESET condition.
self refresh exit.
in a given tFAW(min) period. tRRD(min) restriction still
applies. The tFAW(min) parameter applies to all 8 bank
DDR2 devices, regardless of the number of banks already
open or closed.
command is issued, regardless of the number of banks
already open or closed. If a single-bank PRECHARGE
command is issued, tRP timing applies. tRPA(MIN)
applies to all 8-bank DDR2 devices.
registrations.
require additional time due to Write recovery time (tWR)
during auto precharge.
on three consecutive positive clock edges. CKE must
remain at the valid input level the entire time it takes to
achieve the 3 clocks of registration. Thus, after any CKE
transition, CKE may not transition from its valid level
during the time period of tIS + 2 * tCK + tIH.
level, but specified whwen the device output is no longer
driving (tRPST) or beginning to drive (tRPRE).
reduced by 100ps.
240-PIN RDIMM