SL72P8M64M8M-A05AYU STEC, SL72P8M64M8M-A05AYU Datasheet - Page 11

• Manufacturer Part Number: SL72P8M64M8M-A05AYU
• Manufacturer: STEC

Specifications of SL72P8M64M8M-A05AYU

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Access Time (max): 600ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.17A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

SL72P8M64M8M-A05AY(W)U
IDD SPECIFICATIONS AND CONDITIONS
IDD specifications are tested after the device is properly
initialized. Recommended Operating Temperature. VDD =
+1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VDDL = +1.8V ±0.1V, VREF
= VDDQ/ 2.
Input slew rate is specified by AC Parametric Test Conditions.
IDD parameters are specified with ODT disabled. Data bus
consists of DQ, DQS, and /DQS. IDD values must be met with
all combinations of EMR bits 10 and 11.
General IDD Parameters
IDD7 Conditions
IDD7: Operating Current, specifies detailed timing
requirements for IDD7. Changes will be required if timing
parameter changes are made to the specification.
Speed Grade
DDR2-400
IDD Parameter
CL (IDD)
tRCD (IDD)
tRC (IDD)
tRRD (IDD)
tCK (IDD)
tRAS MIN (IDD)
tRAS MAX (IDD)
tRP (IDD)
tRFC (IDD)
IDD7 Timing Patterns
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D
Document Part Number 61000-03657-105 November 2007 Page 11
DDR2-400
Definitions for IDD Conditions:
•
•
•
•
•
•
IDD7 Operating Current
All Bank Interleave Read operation; legend: A = active;
RA = read auto precharge; D = deselect
All device banks are being interleaved at minimum tRC (IDD)
without violating tRRD (IDD) using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTs.
IOUT = 0mA.
70,000
105
7.5
15
55
40
15
LOW is defined as VIN<=VIL (AC) (MAX)
HIGH is defined as VIN>=VIH (AC) (MIN)
STABLE is defined as inputs stable at a HIGH or LOW
level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as inputs changing between
HIGH and LOW every other clock cycle (once per two
clocks) for address and control signals
Switching is defined as inputs changing between HIGH
and LOW every other data transfer (once per clock) for
DQ signals not including masks or strobes
3
5
(IDD Specifications and Conditions continued on next page)
Units
tCK
ns
ns
ns
ns
ns
ns
ns
ns
240-PIN RDIMM