SL72P8M64M8M-A05AYU STEC, SL72P8M64M8M-A05AYU Datasheet - Page 17

• Manufacturer Part Number: SL72P8M64M8M-A05AYU
• Manufacturer: STEC

Specifications of SL72P8M64M8M-A05AYU

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Access Time (max): 600ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.17A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

SL72P8M64M8M-A05AY(W)U
REGISTER ELECTRICAL CHARACTERISTICS
Recommended Operating Temperature Range; VDD=VDDQ=+1.8V ±0.1V unless otherwise stated.
REGISTER TIMING REQUIREMENTS
Recommended Operating Temperature Range; VDD=+1.8V ±0.1V
REGISTER SWITCHING CHARACTERISTICS
Recommended Operating Temperature Range; VDD=+1.8V ±0.1V
Symbol Parameters
VIH(DC) DC High-Level Input
VIL(DC) DC Low-Level Input
VIH(AC) AC High-Level Input
VIL(AC) AC Low-Level Input
VOH
VOL
I
IDD
IDDD
CI
CI
Symbol
fclock
tS
tH
Symbol
fmax
tPDM
tPDMSS
tPHL
I
1
Voltage for
Addr/Ctrl/Cmd
Voltage for
Addr/Ctrl/Cmd
Voltage for
Addr/Ctrl/Cmd
Voltage for
Addr/Ctrl/Cmd
Output High Voltage
for PAR_IN
Output Low Voltage
for PAR_IN
Input Current for All
Inputs
Standby (Static)
Operating (Static)
Dynamic Operating
(Clock Only)
Dynamic Operating
(Per Each Data Input) VI = VIH(AC) or VIL (AC),
Input Capacitance all
pins except /RESET
Input Capacitance for
/RESET
Parameters
Clock Frequency
Setup Time
Hold Time
From (Input) To (Output)
CK, /CK
CK, /CK
/RESET
Conditions
SSTL_18
SSTL_18
SSTL_18
SSTL_18
IOH = -6mA
IOL = 6mA
VI = VDD or GND
/RESET = GND, IO = 0
VI = VIH(AC) or VIL(AC),
/RESET = VDD, IO = 0,
VI = VIH(AC) or VIL(AC),
CLK and /CLK switching
50% duty cycle.
CLK and /CLK switching
50% duty cycle. One data
input switching at half clock
VI = VREF ±250mV
(PCB not included)
VI = VDDQ or GND
(PCB not included)
Inputs before CK going high, /CK going low
Inputs after CK going low, /CK going high
/RESET = VDD, IO = 0
Q
Q
Q
/RESET = VDD, IO = 0
1.25
Min
410
Typ
Max
1.8
2
3
Document Part Number 61000-03657-105 November 2007 Page 17
VDD/VDDQ
Units
MHz
ns
ns
ns
1.7V
1.7V
1.9V
1.9V
1.9V
1.8V
1.8V
VREF(DC)+125
VREF(DC)+250
0.05
0.05
Min
Min
1.2
2.5
1.6
0
0
Max
410
Typ
VREF(DC)-125
VREF(DC)-250
Units
MHz
240-PIN RDIMM
VDDQ+250
ns
ns
18 (1:1)
28 (1:2)
VDD
Max
0.5
0.5
3.5
±5
75
85
2
MHz/data
µA/clock
µ/clock
Units
MHz
mV
mV
mV
mV
mV
mV
mA
mA
µA
pF
pF