TC59LM818DMBI-37 Toshiba, TC59LM818DMBI-37 Datasheet - Page 35

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TC59LM818DMBI-37

Manufacturer Part Number
TC59LM818DMBI-37
Description
Manufacturer
Toshiba
Type
DDR FCRAMr
Datasheet

Specifications of TC59LM818DMBI-37

Organization
16Mx18
Density
288Mb
Address Bus
17b
Access Time (max)
650ps
Maximum Clock Rate
533MHz
Operating Supply Voltage (typ)
2.5V
Package Type
BGA
Operating Temp Range
-40C to 100C
Operating Supply Voltage (max)
2.625V
Operating Supply Voltage (min)
2.375V
Supply Current
420mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant
Unidirectional DS/QS mode
Unidirectional DS/Free Running QS mode
Bank Add.
BL = 2
BL = 4
BL = 2
BL = 4
Command
MULTIPLE BANK WRITE TIMING (CL = 5)
Address
(output)
(output)
(output)
(output)
(input)
(input)
(input)
(input)
(input)
(input)
(input)
(input)
CLK
CLK
DQ
DQ
DQ
DQ
QS
QS
QS
QS
DS
DS
DS
DS
Note: l
WRA
Bank
UA
"a"
0
I
RBD
Low
Low
RC
= 2 cycles
to the same bank must be satisfied.
LAL
LA
1
I
RC
WRA
Bank
UA
"b"
(Bank"a") = 6 cycles
2
WL = 4
WL = 4
WL = 4
WL = 4
LAL
LA
3
I
RC
(Bank"b") = 6 cycles
4
DESL
WL = 4
WL = 4
WL = 4
WL = 4
Da0Da1
Da0Da1
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1Db2Db3
5
WRA
I
Bank
RBD
UA
"a"
6
= 2 cycles I
LAL
Db0Db1
Db0Db1
LA
7
WRA
Bank
UA
"b"
8
RBD
= 2 cycles I
LAL
LA
9
WRA
Bank
UA
"c"
10
RBD
TC59LM818DMBI-37
LAL
Da0 Da1
Da0 Da1 Da2 Da3 Db0 Db1 Db2Db3Dc0 Dc1
Da0 Da1
Da0 Da1 Da2 Da3 Db0 Db1 Db2Db3Dc0 Dc1
= 2 cycles I
LA
11
WRA
Bank
2005-03-07 35/55
UA
"d"
12
RBD
LAL
Db0 Db1
Db0 Db1
LA
13
= 2 cycles
WRA
Bank
UA
"a"
14
Rev 1.2
LAL
Dc0Dc1
Dc0Dc1
LA
15

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