TC59LM818DMBI-37 Toshiba, TC59LM818DMBI-37 Datasheet - Page 49

• Manufacturer Part Number: TC59LM818DMBI-37
• Manufacturer: Toshiba
• Type: DDR FCRAMr

Specifications of TC59LM818DMBI-37

• Organization: 16Mx18
• Density: 288Mb
• Address Bus: 17b
• Access Time (max): 650ps
• Maximum Clock Rate: 533MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: BGA
• Operating Temp Range: -40C to 100C
• Operating Supply Voltage (max): 2.625V
• Operating Supply Voltage (min): 2.375V
• Supply Current: 420mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

COMMAND FUNCTIONS and OPERATIONS
mode, each operation mode decided by the combination of the first command and the second command from
stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the next clock of the
RDA command, the data is read out sequentially synchronizing with the both edges of QS output signal (Burst
Read Operation). The initial valid read data appears after CAS latency from the issuing of the LAL command.
The valid data is outputted for a burst length. The CAS latency, the burst length of read data and the burst type
must be set in the Mode Register beforehand. The read operated bank goes back automatically to the idle state
after l
Write Operation (1st command + 2nd command = WRA + LAL)
by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the next clock of the
WRA command, the input data is latched sequentially synchronizing with the both edges of DS input signal (Burst
Write Operation). The data and DS inputs have to be asserted in keeping with clock input after CAS latency-1
from the issuing of the LAL command. The DS has to be provided for a burst length. The CAS latency and the
burst type must be set in the Mode Register beforehand. The write operated bank goes back automatically to the
idle state after l
table.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
REF command following to the WRA command. In a point to notice, the write mode started with the WRA
command is canceled by the REF command having gone into the next clock of the WRA command instead of the
LAL command. The minimum period between the Auto-Refresh command and the next command is specified by
l
distributed refresh, Auto-Refresh command has to be issued within once for every 1.95 µs by the maximum. In case
of burst refresh or random distributed refresh, the average interval of eight consecutive Auto-Refresh commands
has to be more than 400 ns always. In other words, the number of Auto-Refresh cycles that can be performed within
3.2 µs (8 × 400 ns) is to 8 times in the maximum.
Power Down Mode (
Down Mode by asserting PD is “Low”. When the device enters the Power Down Mode, all input and output buffers
are disabled after specified time except for PD , CLK, CLK and QS. Therefore, the power dissipation lowers. To
exit the Power Down Mode, PD has to be brought to “High” and the DESL command has to be issued for l
cycle after PD goes high. The Power Down exit function is asynchronous operation.
REFC
TC59LM818DMBI are introduced the two consecutive command input method. Therefore, except for Power Down
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated
TC59LM818DMBI are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the
When all banks are in the idle state and DQ outputs are in Hi-Z states, the TC59LM818DMBI become Power
RC
. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In case of equally
.
RC
. Write Burst Length is controlled by VW0 and VW1 inputs with LAL command. See VW truth
PD
= “L”)
TC59LM818DMBI-37
2005-03-07 49/55
Rev 1.2
PDA