TC59LM818DMBI-37 Toshiba, TC59LM818DMBI-37 Datasheet - Page 6

• Manufacturer Part Number: TC59LM818DMBI-37
• Manufacturer: Toshiba
• Type: DDR FCRAMr

Specifications of TC59LM818DMBI-37

• Organization: 16Mx18
• Density: 288Mb
• Address Bus: 17b
• Access Time (max): 650ps
• Maximum Clock Rate: 533MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: BGA
• Operating Temp Range: -40C to 100C
• Operating Supply Voltage (max): 2.625V
• Operating Supply Voltage (min): 2.375V
• Supply Current: 420mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

RECOMMENDED DC OPERATING CONDITIONS
(V
I
I
I
I
I
I
Notes: 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of
DD1S
DD2N
DD2P
DD4W
DD4R
DD5B
DD
SYMBOL
= 2.5 V ± 0.125 V, V
2. These parameters define the current between V
3. I
specification.
t
DD5B
CK
, t
Operating Current
One bank read or write operation ;
t
Burst Length = 4, CAS Latency = 6, Free running QS mode ;
0 V ≤ V
Address inputs change up to 2 times during minimum I
Read data change twice per clock cycle
Standby Current
All banks: inactive state ;
t
0 V ≤ V
Other input signals change one time during 4 × t
DQ and DS inputs change twice per clock cycle
Standby (power down) Current
All banks: inactive state ;
t
CAS Latency = 6, Free running QS mode ;
0 V ≤ V
Other input signals change one time during 4 × t
DQ and DS inputs are floating (V
Write Operating Current (4Banks)
4 Bank interleaved continuous burst write operation ;
t
Burst Length = 4, CAS Latency = 6, Free running QS mode ;
0 V ≤ V
Address inputs change once per clock cycle,
DQ and DS inputs change twice per clock cycle
Read Operating Current (4Banks)
4 Bank interleaved continuous burst read operation ;
t
Burst Length = 4, CAS Latency = 6, Free running QS mode ;
0 V ≤ V
Address inputs change once per clock cycle,
Read data change twice per clock cycle
Burst Auto Refresh Current
Refresh command at every I
t
CAS Latency = 6, Free running QS mode ;
0 V ≤ V
Address inputs change up to 2 times during minimum I
DQ and DS inputs change twice per clock cycle
CK
CK
CK
CK
CK
CK
RC
is specified under burst refresh condition. Actual system should use distributed refresh that meet to t
= min; I
= min, CS = V
= min, PD = V
= min, I
= min, I
= min; I
and I
IN
IN
IN
IN
IN
IN
RC
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
RC
RC
RC
REFC
.
IL
IL
IL
IL
IL
IL
= min, I
= min ;
= min, I
(AC) (max), V
(AC) (max), V
(AC) (max), V
(AC) (max), V
(AC) (max), V
(AC) (max), V
DDQ
= min ;
IH
IL
, PD = V
(power down) ;
OUT
OUT
= 1.7 V
PARAMETER
= 0mA ;
= 0mA ;
REFC
IH
IH
IH
IH
IH
IH
(AC) (min) ≤ V
(AC) (min) ≤ V
(AC) (min) ≤ V
(AC) (min) ≤ V
(AC) (min) ≤ V
(AC) (min) ≤ V
IH
DDQ
~
interval ;
;
1.9 V, T
/2)
DD
IN
IN
IN
IN
IN
IN
and V
CASE
CK
CK
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
,
,
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
SS
RC
REFC
= −40 ~ 100°C)
.
,
,
,
;
;
;
;
,
MAX
220
420
420
220
-37
95
65
TC59LM818DMBI-37
2005-03-07 6/55
UNIT
mA
NOTES
Rev 1.2
1, 2, 3
1, 2
1, 2
1, 2
1, 2
1, 2
REFI