LFXP6C-4QN208I Lattice, LFXP6C-4QN208I Datasheet - Page 150

• Manufacturer Part Number: LFXP6C-4QN208I
• Description: FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
• Manufacturer: Lattice

Specifications of LFXP6C-4QN208I

• Package: 208PQFP
• Family Name: LatticeXP
• Device Logic Units: 6000
• Maximum Internal Frequency: 360 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 142
• Ram Bits: 73728
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 8-6. I/O_TYPE Attribute Values
OPENDRAIN
LVCMOS and LVTTL I/O standards can be set to Open Drain configuration by using the OPENDRAIN attribute.
Values: ON, OFF
Default: OFF
DRIVE
The drive strength attribute is available for LVTTL and LVCMOS output standards. These can be set or each I/O pin
individually.
DEFAULT (for LatticeECP/EC)
DEFAULT (for LatticeXP)
LVDS 2.5V
RSDS
Emulated LVDS 2.5V
Bus LVDS 2.5V
LVPECL 3.3V
HSTL18 Class I, II and III
Differential HSTL 18 Class I, II and III
HSTL 15 Class I and III
Differential HSTL 15 Class I and III
SSTL 33 Class I and II
Differential SSTL 33 Class I and II
SSTL 25 Class I and II
Differential SSTL 25 Class I and II
SSTL 18 Class I
Differential SSTL 18 Class I
LVTTL
3.3V LVCMOS
2.5V LVCMOS
1.8V LVCMOS
1.5V LVCMOS
1.2V LVCMOS
3.3V PCI
1. These differential standards are implemented by using complementary 
LVCMOS driver with external resistor pack.
sysIO Signaling Standard
8-10
LVDS25
RSDS
LVDS25E
BLVDS25
HSTL18_I,
HSTL18_II,
HSTL18_III
HSTL18D_I
HSTL18D_II
HSTL18D_III
HSTL15_I
HSTL15_III
HSTL15D_I
HSTL15D_III
SSTL33_I,
SSTL33_II
SSTL33D_I
SSTL3D_II
SSTL25_I
SSTL25_II
SSTL25D_I
SSTL25D_II
SSTL18_I
SSTL18D_I
LVTTL33
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33
LVPECL33
LVCMOS12
LVCMOS25
IO_TYPE
1
1
1
LatticeECP/EC and LatticeXP
sysIO Usage Guide