LFXP6C-4QN208I Lattice, LFXP6C-4QN208I Datasheet - Page 264

• Manufacturer Part Number: LFXP6C-4QN208I
• Description: FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
• Manufacturer: Lattice

Specifications of LFXP6C-4QN208I

• Package: 208PQFP
• Family Name: LatticeXP
• Device Logic Units: 6000
• Maximum Internal Frequency: 360 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 142
• Ram Bits: 73728
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
Figure 11-6. IPexpress Main Window
Configuration Tab
The Configuration Tab lists all user accessible attributes. Default values are set initially.
There are two modes in the Configuration Tab which can be used to configure the PLL, Frequency Mode and
Divider Mode.
Frequency Mode: In this mode, the user enters input and output clock frequencies and the software calculates the
divider settings for the user. If the output frequency the user entered is not achievable, the nearest frequency will be
displayed in the ‘Actual’ text box. After input and output frequencies are entered, clicking the ‘Calculate’ button will
display the divider values. If the desired output frequency is not achievable with the given frequency tolerance, the
software generates an error. Users may increase the frequency tolerance or change the output frequencies.
Figure 11-7 shows the Configuration Tab window.
11-8