LFXP6C-4QN208I Lattice, LFXP6C-4QN208I Datasheet - Page 201

• Manufacturer Part Number: LFXP6C-4QN208I
• Description: FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
• Manufacturer: Lattice

Specifications of LFXP6C-4QN208I

• Package: 208PQFP
• Family Name: LatticeXP
• Device Logic Units: 6000
• Maximum Internal Frequency: 360 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 142
• Ram Bits: 73728
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 9-40. FIFO with Output Registers, End of Data Read Cycle
And finally, if you select the option enable output register with RdEn, it still delays the data out by one clock cycle
(as compared to the non-pipelined FIFO), and the RdEn should be high also during that clock cycle, otherwise the
data takes an extra clock cycle when the RdEn goes true.
Figure 9-41. FIFO with Output Registers and RdEn on Output Registers
Almost Full
Almost
Almost
Empty
Empty
Almost
Reset
Clock
WrEn
RdEn
Reset
Empty
Empty
Clock
WrEn
RdEn
Data
Data
Full
Full
Full
Q
Q
Invalid Data
Data_N-5
Data_1
Data_N-4
Data_2
Invalid Data
Data_N-3
9-36
Invalid Data
Data_3
Data_N-2
LatticeECP/EC and LatticeXP Devices
Data_4
Data_N-1
Data_1
Data_5
Memory Usage Guide
Data_N
Data_2