LFXP6C-4QN208I Lattice, LFXP6C-4QN208I Datasheet - Page 338

• Manufacturer Part Number: LFXP6C-4QN208I
• Description: FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
• Manufacturer: Lattice

Specifications of LFXP6C-4QN208I

• Package: 208PQFP
• Family Name: LatticeXP
• Device Logic Units: 6000
• Maximum Internal Frequency: 360 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 142
• Ram Bits: 73728
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
The following are the HDL representations of the design in Figure 13-7.
The preferable way is to fully employ the PFU's natural “Ripple-mode”. A single PFU can support up to 8-bit ripple
functions with fast carry logic. Figure 13-8 is an example of 4-bit counter in PFU “Ripple Mode”. In Lattice Semicon-
ductor FPGA architectures, an internal generated clock can get on the clock spine for small skew clock distribution,
further enhancing the performance of the clock divider.
Figure 13-8. Use PFU “Ripple Mode”
Here are the HDL representations of the design in Figure 13-8.
-- VHDL Example of Daisy Chaining FF
...
-- 1st FF to divide Clock in half
CLK_DIV1: process(CLK, RST)
begin
end process CLK_DIV1;
-- 2nd FF to divide clock in half
CLK_DIV2: process(clk1, RST)
begin
end process CLK_DIV2;
-- VHDL : “RippleMode” Clock Divider
...
COUNT4: process(CLK, RST)
begin
end process COUNT4;
DIVBY4
DIVBY16 <= cnt(3);
if (RST='1') then
elsif (CLK'event and CLK='1') then
end if;
if (RST='1') then
elsif (clk1'event and clk1='1') then
end if;
if (RST='1') then
elsif (CLK'event and CLK='1') then
end if;
clk1 <= '0';
clk1 <= not clk1;
clk2 <= '0';
clk2 <= not clk2;
cnt <= (others=>'0');
cnt <= cnt + 1;
<= cnt(1);
Ripple Mode
Counter
LUT in
4-Bit
13-11
//Verilog : “RippleMode” Clock Divider
...
always @(posedge CLK or posedge RST)
begin
end
assign DIVBY4
assign DIVBY16 = cnt[3];
...
//Verilog Example of Daisy Chaining FF
...
always @(posedge CLK or posedge RST)
begin
end
always @(posedge clk1 or posedge RST)
begin
end
...
if (RST)
else
if (RST)
else
if (RST)
else
cnt = 4'b0;
cnt = cnt + 1'b1;
clk1 = 1'b0;
clk1 = !clk1;
clk2 = 1'b0;
clk2 = !clk2;
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
= cnt[1];
DIVBY2
DIVBY4
DIVBY8
DIVBY16