LFXP6C-4QN208I Lattice, LFXP6C-4QN208I Datasheet - Page 212
LFXP6C-4QN208I
Manufacturer Part Number
LFXP6C-4QN208I
Description
FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
Manufacturer
Lattice
Specifications of LFXP6C-4QN208I
Package
208PQFP
Family Name
LatticeXP
Device Logic Units
6000
Maximum Internal Frequency
360 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
142
Ram Bits
73728
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-4QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 9-56. PFU-based Distributed Dual Port RAM for LatticeECP/EC and LatticeXP Devices
Ports such as Read Clock (RdClock) and Read Clock Enable (RdClockEn) are not available in the hardware primi-
tive. These are generated by IPexpress when the user wants the to enable the output registers in the IPexpress
configuration.
The various ports and their definitions for the memory are included in Table 9-15. The table lists the corresponding
ports for the module generated by IPexpress and for the primitive.
Table 9-15. PFU-based Distributed Dual-Port RAM Port Definitions
Users have the option of enabling the output registers for Distributed Dual Port RAM (Distributed_DPRAM). Fig-
ures 8-39 and 8-40 show the internal timing waveforms for the Distributed Dual Port RAM (Distributed_DPRAM)
with these options.
WrAddress
RdAddress
RdClock
RdClockEn
WrClock
WrClockEn
WE
Data
Q
Generated Module
Port Name in
WAD[23:0]
RAD[3:0]
—
—
WCK
—
WRE
DI[1:0]
RDO[1:0]
WAD[3:0]
RAD[3:0]
EBR Block Primitive
DI[1:0]
WCK
WRE
Port Name in
PFU
9-47
Write Address
Read Address
Read Clock
Read Clock Enable
Write Clock
Write Clock Enable
Write Enable
Data Input
Data Out
LatticeECP/EC and LatticeXP Devices
Description
WDO[1:0]
RDO[1:0]
—
—
Rising Clock Edge
Active High
Rising Clock Edge
Active High
Active High
—
—
Memory Usage Guide
Active State
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