LFXP6C-4QN208I Lattice, LFXP6C-4QN208I Datasheet - Page 347

• Manufacturer Part Number: LFXP6C-4QN208I
• Description: FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
• Manufacturer: Lattice

Specifications of LFXP6C-4QN208I

• Package: 208PQFP
• Family Name: LatticeXP
• Device Logic Units: 6000
• Maximum Internal Frequency: 360 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 142
• Ram Bits: 73728
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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Proper Preferences
Providing proper preferences is key to a successful design. If the constraints of a preference file are tighter than the
system requirements, the design will end up being over-constrained. As a consequence, PAR run times will be con-
siderably longer. In addition, over-constraining non-critical paths will force PAR to waste unnecessary processing
power trying to meet these constraints, hence creating possible conflicts with real critical paths that ought to be
optimized first.
On the other hand, if a preference file is under-constrained compared to real system requirements, real timing
issues not previously seen during dynamic timing simulations and static timing analysis could be observed on a
test board, or during production.
Common causes of over-constrained timing preferences include:
Note that over-constrained designs will also need a significantly larger amount of processing power and computing
resources. As a result, it might be necessary to increase some of the allocated system resources (as in increasing
your PC virtual memory paging size).
Common causes of under-constrained timing preferences include:
In general, to make sure that no critical paths were left out due to under-constraining, it is recommended to check
for path coverage at the end of a Trace report file (.twr).
An example of such an output is shown in Figure 17-1.
Figure 17-1. Trace Report (.twr) Timing Summary Example
• Block Asynchronous Paths: Prevents the timing tools from analyzing any paths from input pads to regis-
• Block RAM Reads during Write: If using PFU based RAM, this will prevent timing analysis on a RAM read
• Frequency/Period <net>: Each clock net in the design should contain a frequency or period preference.
• Input Setup: Each synchronous input should have an input_setup preference.
• Clock-to-Out: Each synchronous output should have a clock_to_out preference.
• Block <net>: All asynchronous reset nets in the design should be blocked.
• Multicycle: The multicycle preference allows the designer to relax a frequency/period constraint on
• Multicycle paths not specified.
• Multiple paths to/from I/Os with different specifications.
• Attempt to fool the PAR tool with tighter than necessary specifications.
• I/O specifications not defined.
• Asynchronous logic without MAXDELAY preferences.
• Internally generated or unintentional clocks not specified in preference file.
• Blocking critical paths.
ters or from input pads to output pads.
during a write on the same address in a single clock period.
selected paths.
Timing summary:
---------------
Timing errors: 4096
Constraints cover 36575 paths, 6 nets, and 8635 connections (99.0% coverage)
Score: 25326584
17-3
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