LFXP6C-4QN208I Lattice, LFXP6C-4QN208I Datasheet - Page 190

• Manufacturer Part Number: LFXP6C-4QN208I
• Description: FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
• Manufacturer: Lattice

Specifications of LFXP6C-4QN208I

• Package: 208PQFP
• Family Name: LatticeXP
• Device Logic Units: 6000
• Maximum Internal Frequency: 360 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 142
• Ram Bits: 73728
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 9-26. PSEUDO DUAL PORT RAM Timing Diagram – with Output Registers
Read Only Memory (ROM) – EBR Based
The EBR blocks in the LatticeECP/EC and LatticeXP devices can be configured as Read Only Memory or ROM.
IPexpress allows users to generate the Verilog-HDL or VHDL along with an EDIF netlist for the memory size as per
design requirements. Users are required to provide the ROM memory content in the form of an initialization file.
IPexpress generates the memory module as shown in Figure 9-27.
Figure 9-27. ROM - Read Only Memory Module Generated by IPexpress
The generated module makes use of these EBR blocks or primitives. For memory sizes smaller than an EBR block,
the module will be created in one EBR block. If the specified memory is larger than one EBR block, multiple EBR
blocks can be cascaded, in depth or width (as required to create these sizes).
The basic ROM primitive for the LatticeECP/EC and LatticeXP devices is as shown in Figure 9-28.
WrClockEn
RdClockEn
WrAddress
RdAddress
WrClock
RdClock
Data
Q
t
t
SUADDR_EBR
SUADDR_EBR
t
SUDATA_EBR
t
SUCE_EBR
Data_0
Add_0
OutClockEn
t
t
t
OutClock
HADDR_EBR
HADDR_EBR
HDATA_EBR
Address
Reset
Data_1
Add_1
Invalid Data
EBR based Read Only
t
SUCE_EBR
9-25
Memory
ROM
Add_0
LatticeECP/EC and LatticeXP Devices
t
HCE_EBR
Q
Add_1
Memory Usage Guide
t
COO_EBR
Data_2
Add_2
Data_0
Add_2
t
HCE_EBR
Dat
a_1