XC56309AG100A Freescale Semiconductor, XC56309AG100A Datasheet - Page 34

• Manufacturer Part Number: XC56309AG100A
• Description: IC DSP 24BIT 100MHZ 144-TQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309AG100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signals/Connections
2.7.1 Host Port Usage Considerations
Careful synchronization is required when the system reads multiple-bit registers that are written
by another asynchronous system. This is a common problem when two asynchronous systems are
connected (as they are in the Host port). The considerations for proper operation are discussed in
Table 2-10.
2.7.2 Host Port Configuration
HI08 signal functions vary according to the programmed configuration of the interface as
determined by the 16 bits in the HI08 Port Control Register (HPCR). Refer to the Chapter 6,
Host Interface (HI08), for detailed descriptions of HI08 configuration registers.
2-10
H[0–7]
HAD[0–7]
PB[0–7]
Asynchronous read of receive
byte registers
Asynchronous write to
transmit byte registers
Asynchronous write to host
vector
Signal Name
Action
Input/Output
Input/Output
Input or
Output
Type
To assure that the data in the receive byte registers is valid when you are reading the r
Receive register High (RXH), Receive register Middle (RXM), or Receive register Low (RXL),
use interrupts or poll the Receive Register Data Full (RXDF) flag that indicates data is
available.
To ensure that the transmit byte registers transfer valid data to the Host Receive (HRX)
register, do not write to the Transmit register High (TXH), Transmit register Middle (TXM), or
Transmit register Low (TXL) registers unless the Transmit register Data Empty (TXDE) bit is
set indicating that the transmit byte registers are empty.
To ensure that the DSP interrupt control logic receives a stable vector, change the Host
Vector (HV) register only when the Host Command bit (HC) is clear.
Table 2-10. Host Port Usage Considerations
State During
Ignored input
Reset
1,2
Table 2-11. Host Interface
DSP56309 User’s Manual, Rev. 1
Host Data
When the HI08 is programmed to interface with a non-multiplexed host
bus and the HI function is selected, these signals are lines 0–7 of the Data
bus.
Host Address
When the HI08 is programmed to interface with a multiplexed host bus
and the HI function is selected, these signals are lines 0–7 of the
Address/Data bus.
Port B 0–7
When the HI08 is configured as GPIO through the HPCR, these signals
are individually programmed through the HI08 Data Direction Register
(HDDR). This input is 5 V tolerant.
Description
Signal Description
Freescale Semiconductor