XC5VLX50-1FFG1153C Xilinx Inc, XC5VLX50-1FFG1153C Datasheet - Page 104

• Manufacturer Part Number: XC5VLX50-1FFG1153C
• Description: IC FPGA VIRTEX-5 50K 1153FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG1153C

• Total Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 560
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1153-BBGA, FCBGA
• No. Of Logic Blocks: 3600
• No. Of Macrocells: 50000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 560
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1561

Chapter 3: Phase-Locked Loops (PLLs)
Reference Clock Switching
104
X-Ref Target - Figure 3-8
All “O” counters are equivalent, anything O0 can do, O1 can do. The PLL outputs are
flexible when connecting to the global clock network since they are identical. In most cases,
this level of detail is imperceptible to the designer as the software and PLL Wizard
determines the proper settings through the PLL attributes and Wizard inputs.
The PLL reference clock can be dynamically switched by using the CLKINSEL pin. The
switching is done asynchronously. Since the clock signal can generate a narrow pulse
resulting in erroneous behavior of the PLL, the PLL should be held in RESET while
selecting the alternate clock with the CLKINSEL (CLKSRC) signal. The PLL clock mux
switching is shown in
mux. No synchronization logic is present.
X-Ref Target - Figure 3-9
8 Phases
Counter
Outputs
VCO
135°
180°
225°
270°
315°
45°
90°
O0
O1
O2
O3
0°
One Cycle Delay
Figure
CLKSRC
CLKIN1
CLKIN2
www.xilinx.com
IBUFG
IBUFG
Figure 3-8: Selecting VCO Phases
BUFG
BUFG
Figure 3-9: Input Clock Switching
DCM
DCM
3-9. The CLKINSEL (CLKSRC) signal directly controls the
ug190_3_09_050906
PLL
CLKIN
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_03_08_032506