XC5VLX50-1FFG1153C Xilinx Inc, XC5VLX50-1FFG1153C Datasheet - Page 106

• Manufacturer Part Number: XC5VLX50-1FFG1153C
• Description: IC FPGA VIRTEX-5 50K 1153FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG1153C

• Total Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 560
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1153-BBGA, FCBGA
• No. Of Logic Blocks: 3600
• No. Of Macrocells: 50000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 560
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1561

Chapter 3: Phase-Locked Loops (PLLs)
106
Zero Delay Buffer
PLL with Internal Feedback
The PLL feedback can be internal to the PLL when the PLL is used as a synthesizer or jitter
filter and there is no required phase relationship between the PLL input clock and the PLL
output clock. The PLL performance should increase since the feedback clock is not
subjected to noise on the core supply since it never passes through a block powered by this
supply. Of course, noise introduced on the CLKIN signal and the BUFG will still be present
(Figure
X-Ref Target - Figure 3-11
The PLL can also be used to generate a zero delay buffer clock. A zero delay buffer can be
useful for applications where there is a single clock signal fan out to multiple destinations
with a low skew between them. This configuration is shown in the
feedback signal drives off chip and the board trace feedback is designed to match the trace
to the external components. In this configuration, it is assumed that the clock edges are
aligned at the input of the FPGA and the input of the external component. There will be a
limitation on the maximum delay allowed in the feedback path.
X-Ref Target - Figure 3-12
3-11).
IBUFG
IBUFG
Figure 3-11: PLL with Internal Feedback
CLKIN1
CLKFBIN
RST
PLL
www.xilinx.com
Inside FPGA
Figure 3-12: Zero Delay Buffer
CLKFBOUT
CLKIN1
CLKFBIN
RST
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
PLL
CLKFBOUT
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
BUFG
BUFG
BUFG
OBUF
UG190_3_11_040906
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
To Logic
Figure
UG190_3_12_120108
3-12. Here, the
To
External
Components