XC5VLX50-1FFG1153C Xilinx Inc, XC5VLX50-1FFG1153C Datasheet - Page 215

• Manufacturer Part Number: XC5VLX50-1FFG1153C
• Description: IC FPGA VIRTEX-5 50K 1153FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG1153C

• Total Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 560
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1153-BBGA, FCBGA
• No. Of Logic Blocks: 3600
• No. Of Macrocells: 50000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 560
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1561

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Multiplexer Primitives
Carry Chain Primitive
Port Signals
X-Ref Target - Figure 5-35
Two primitives (MUXF7 and MUXF8) are available for access to the dedicated F7AMUX,
F7BMUX and F8MUX in each slice. Combined with LUTs, these multiplexer primitives are
also used to build larger width multiplexers (from 8:1 to 16:1). The
Multiplexers
Data In – I0, I1
The data input provides the data to be selected by the select signal (S).
Control In – S
The select input signal determines the data input signal to be connected to the output O.
Logic 0 selects the I0 input, while logic 1 selects the I1 input.
Data Out – O
The data output O provides the data value (one bit) selected by the control inputs.
The CARRY4 primitive represents the fast carry logic for a slice in the Virtex-5 architecture.
This primitive works in conjunction with LUTs in order to build adders and multipliers.
This primitive is generally inferred by synthesis tools from standard RTL code. The
synthesis tool can identify the arithmetic and/or logic functionality that best maps to this
00111
D
5
D
D
D
A[4:0]
SRLC32G
SRLC32G
SRLC32G
section provides more information on building larger multiplexers.
LUT
LUT
LUT
Figure 5-35: Example Static-Length Shift Register
Q31
Q31
Q31
Q
www.xilinx.com
OUT
(72-bit SRL)
00110
D
5
D
SRLC32G
D
SRLC32G
D
A[4:0]
SRLC32G
LUT
LUT
LUT
Q31
Q31
Q31
Q
D
Designing Large
FF
Q
CLB Primitives
UG190_5_35_050506
OUT
(72-bit SRL)
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