XC5VLX50-1FFG1153C Xilinx Inc, XC5VLX50-1FFG1153C Datasheet - Page 89

• Manufacturer Part Number: XC5VLX50-1FFG1153C
• Description: IC FPGA VIRTEX-5 50K 1153FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG1153C

• Total Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 560
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1153-BBGA, FCBGA
• No. Of Logic Blocks: 3600
• No. Of Macrocells: 50000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 560
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1561

Phase-Locked Loops (PLLs)
Introduction
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
The clock management tile (CMT) in Virtex-5 FPGAs includes two DCMs and one PLL.
There are dedicated routes within a CMT to couple together various components. Each
block within the tile can be treated separately, however, there exists a dedicated routing
between blocks creating restrictions on certain connections. Using these dedicated routes
frees up global resources for other design elements. Additionally, the use of local routes
within the CMT provides an improved clock path because the route is handled locally,
reducing chances for noise coupling.
The CMT diagram
various clock input sources and the DCM-to-PLL and PLL-to-DCM dedicated routing. The
six (total) PLL output clocks are muxed into a single clock signal for use as a reference clock
to the DCMs. Two output clocks from the PLL can drive the DCMs. These two clocks are
100% independent. PLL output clock 0 could drive DCM1 while PLL output clock 1 could
drive DCM2. Each DCM output can be muxed into a single clock signal for use as a
reference clock to the PLL. Only one DCM can be used as the reference clock to the PLL at
any given time. A DCM can not be inserted in the feedback path of the PLL. Both the PLLs
or DCMs of a CMT can be used separately as stand-alone functions. The outputs from the
PLL are not spread spectrum.
(Figure
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3-1) shows a high-level view of the connection between the
Chapter 3
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