XC5VLX50-1FFG1153C Xilinx Inc, XC5VLX50-1FFG1153C Datasheet - Page 45

• Manufacturer Part Number: XC5VLX50-1FFG1153C
• Description: IC FPGA VIRTEX-5 50K 1153FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG1153C

• Total Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 560
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1153-BBGA, FCBGA
• No. Of Logic Blocks: 3600
• No. Of Macrocells: 50000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 560
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1561

X-Ref Target - Figure 1-22
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Clock Capable I/O
BUFR Use Models
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
BUFRs are ideal for source-synchronous applications requiring clock domain crossing or
serial-to-parallel conversion. Unlike BUFIOs, BUFRs are capable of clocking logic
resources in the FPGAs other than the IOBs.
Figure 1-22: BUFR Driving Various Logic Resources
BUFIO
BUFR
www.xilinx.com
To Region
Above
To Region
Below
Figure 1-22
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
is a BUFR design example.
Block
Block
RAM
RAM
Regional Clocking Resources
DSP
DSP
Tile
Tile
UG190_c1_22_022609
To Center
of Die
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