XC5VLX50-1FFG1153C Xilinx Inc, XC5VLX50-1FFG1153C Datasheet - Page 251

• Manufacturer Part Number: XC5VLX50-1FFG1153C
• Description: IC FPGA VIRTEX-5 50K 1153FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG1153C

• Total Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 560
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1153-BBGA, FCBGA
• No. Of Logic Blocks: 3600
• No. Of Macrocells: 50000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 560
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1561

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
HSTL_ II_DCI, HSTL_ IV_DCI, HSTL_ II_DCI_18, HSTL_ IV_DCI_18
HSTL_ II_T_DCI, HSTL_ II_T_DCI_18
DIFF_HSTL_ II, DIFF_HSTL_II_18
DIFF_HSTL_II_DCI, DIFF_HSTL_II_DCI_18
DIFF_HSTL_I, DIFF_HSTL_I_18
DIFF_HSTL_I_DCI, DIFF_HSTL_I_DCI_18
HSTL_II_DCI provides on-chip split thevenin termination powered from V
an equivalent termination voltage of V
to V
links.
HSTL_ II_T_DCI and HSTL_ II_T_DCI_18 provide on-chip split-thevenin termination
powered from V
standards are 3-stated. When not 3-stated, these two standards do not have termination.
Differential HSTL class II pairs complimentary single-ended HSTL_II type drivers with a
differential receiver. Differential HSTL class II is intended to be used in bidirectional links.
Differential HSTL can also be used for differential clock and DQS signals in memory
interface designs.
Differential HSTL class II pairs complimentary single-ended HSTL_II type drivers with a
differential receiver, including on-chip differential split-thevenin termination. Differential
HSTL class II is intended to be used in bidirectional links. Differential HSTL can also be
used for differential clock and DQS signals in memory interface designs.
Differential HSTL class I pairs complimentary single-ended HSTL_I type drivers with a
differential receiver. Differential HSTL class I is intended to be used in unidirectional links.
Differential HSTL class I pairs complimentary single-ended HSTL_I type drivers with a
differential receiver, including on-chip differential split-thevenin termination. Differential
HSTL class I is intended to be used in unidirectional links.
CCO
(V
TT
). HSTL_II_DCI and HSTL_IV_ DCI are intended to be used in bidirectional
CCO
that creates an equivalent termination voltage of V
www.xilinx.com
Specific Guidelines for I/O Supported Standards
CCO
/2. HSTL_IV_ DCI provides single termination
CCO
/2 when these
CCO
, creating
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