XC5VLX50-1FFG1153C Xilinx Inc, XC5VLX50-1FFG1153C Datasheet - Page 179

• Manufacturer Part Number: XC5VLX50-1FFG1153C
• Description: IC FPGA VIRTEX-5 50K 1153FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG1153C

• Total Ram Bits: 1769472
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 560
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1153-BBGA, FCBGA
• No. Of Logic Blocks: 3600
• No. Of Macrocells: 50000
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 560
• Clock Management: DCM, PLL
• Core Supply: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1561

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Table 5-3: Truth Table when SRLOW is Used (Default Condition) (Continued)
Table 5-4: Truth Table when SRHIGH is Used
X-Ref Target - Figure 5-5
SRHIGH and SRLOW can be set individually for each storage element in a slice. The choice
of synchronous (SYNC) or asynchronous (ASYNC) set/reset (SRTYPE) cannot be set
individually for each storage element in a slice.
SR
SR
1
1
0
0
1
1
Figure 5-5: Register/Latch Configuration in a Slice
CLK
DX
CX
SR
BX
CE
AX
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LUT D Output
LUT C Output
LUT B Output
LUT A Output
REV
REV
0
1
0
1
0
1
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
SR
SR
SR
SR
DFF
CFF
BFF
AFF
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
REV
REV
REV
REV
Q
Q
Q
Q
UG190_5_05_071207
Reset Type
Sync
Async
No Logic Change
DQ
CQ
BQ
AQ
Function
Function
0
0
0
1
0
CLB Overview
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