EP1S10F484C7N Altera, EP1S10F484C7N Datasheet - Page 11
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484C7N
Manufacturer Part Number
EP1S10F484C7N
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F484C7N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
10570
Family Type
Stratix
No. Of I/o's
335
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
420MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484C7N
Manufacturer:
ALTERA
Quantity:
455
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- Download datasheet (4Mb)
Altera Corporation
July 2005
Note to
(1)
LEs
M512 RAM blocks (32 × 18 bits)
M4K RAM blocks (128 × 36 bits)
M-RAM blocks (4K × 144 bits)
Total RAM bits
DSP blocks
Embedded multipliers
PLLs
Maximum user I/O pins
LEs
M512 RAM blocks (32 × 18 bits)
M4K RAM blocks (128 × 36 bits)
M-RAM blocks (4K × 144 bits)
Total RAM bits
DSP blocks
Embedded multipliers
PLLs
Maximum user I/O pins
Table 1–1. Stratix Device Features — EP1S10, EP1S20, EP1S25, EP1S30
Table 1–2. Stratix Device Features — EP1S40, EP1S60, EP1S80
This parameter lists the total number of 9 × 9-bit multipliers for each device. For the total number of 18 × 18-bit
multipliers per device, divide the total number of 9 × 9-bit multipliers by 2. For the total number of 36 × 36-bit
multipliers per device, divide the total number of 9 × 9-bit multipliers by 8.
Tables 1–1
Feature
Feature
and 1–2:
(1)
(1)
3,423,744
EP1S40
41,250
384
183
112
822
14
12
4
920,448
EP1S10
10,570
426
94
60
48
1
6
6
1,669,248
EP1S20
18,460
194
586
5,215,104
82
10
80
EP1S60
2
6
57,120
1,022
574
292
144
18
12
6
Stratix Device Handbook, Volume 1
1,944,576
EP1S25
25,660
224
138
706
10
80
2
6
7,427,520
EP1S80
79,040
1,238
767
364
176
22
12
3,317,184
9
Introduction
EP1S30
32,470
295
171
726
12
96
10
4
1–3
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