EP1S10F484C7N Altera, EP1S10F484C7N Datasheet - Page 231
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484C7N
Manufacturer Part Number
EP1S10F484C7N
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F484C7N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
10570
Family Type
Stratix
No. Of I/o's
335
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
420MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484C7N
Manufacturer:
ALTERA
Quantity:
455
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Altera Corporation
January 2006
the FPGA device. The Quartus II software calculates the I/O timing for
each I/O standard with a default baseline loading as specified by the I/O
standard.
Altera measures clock-to-output delays (t
minimum voltage, and maximum temperature (PVT) for the 3.3-V LVTTL
I/O standard with 24 mA (default case) current drive strength setting and
fast slew rate setting. I/O adder delays are measured to calculate the t
change at worst-case PVT across all I/O standards and current drive
strength settings with the default loading shown in
page
across worst-case PVT for all I/O standards and drive strength settings.
These three pieces of data are used to predict the timing at the output pin.
Simulation using IBIS models is required to determine the delays on the
PCB traces in addition to the output pin delay timing reported by the
Quartus II software and the timing model in the device handbook.
1.
2.
3.
4.
5.
The Quartus II software reports maximum timing with the conditions
shown in
Figure 4–7 on page 4–62
by the Quartus II output timing.
t
Output Delay Adder for Loading
Simulate the output driver of choice into the generalized test setup
using values from
Record the time to VMEAS.
Simulate the output driver of choice into the actual PCB trace and
load, using the appropriate IBIS input buffer model or an equivalent
capacitance value to represent the load.
Record the time to VMEAS.
Compare the results of steps 2 and 4. The increase or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-input) of the PCB trace.
CO
4–62. Timing derating data for additional loading is taken for t
at pin = t
Table 4–101 on page 4–62
OUTCO
Table 4–101 on page
max for 3.3-V 24 mA LVTTL + I/O Adder +
shows the model of the circuit that is represented
using the proceeding equation.
Stratix Device Handbook, Volume 1
CO
DC & Switching Characteristics
) at worst-case process,
4–62.
Table 4–101 on
CO
4–61
CO
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