EP1S10F484C7N Altera, EP1S10F484C7N Datasheet - Page 45
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484C7N
Manufacturer Part Number
EP1S10F484C7N
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F484C7N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
10570
Family Type
Stratix
No. Of I/o's
335
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
420MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484C7N
Manufacturer:
ALTERA
Quantity:
455
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- Download datasheet (4Mb)
Altera Corporation
July 2005
Table 2–5. M4K RAM Block Configurations (Simple Dual-Port)
Table 2–6. M4K RAM Block Configurations (True Dual-Port)
Read Port
256
128
256
128
512
512
4K
2K
1K
×
×
×
×
×
×
×
256
256
×
×
512
512
4K
2K
1K
Port A
1
2
4
16
32
18
36
8
9
×
×
×
×
×
×
×
16
18
1
2
4
8
9
4K × 1 2K × 2 1K × 4 512 × 8 256 × 16
v
v
v
v
v
v
4K × 1
v
v
v
v
v
v
The memory address depths and output widths can be configured as
4,096 × 1, 2,048 × 2, 1,024 × 4, 512 × 8 (or 512 × 9 bits), 256 × 16 (or
256 × 18 bits), and 128 × 32 (or 128 × 36 bits). The 128 × 32- or 36-bit
configuration is not available in the true dual-port mode. Mixed-width
configurations are also possible, allowing different read and write
widths.
configurations.
When the M4K RAM block is configured as a shift register block, you can
create a shift register up to 4,608 bits (w × m × n).
v
v
v
v
v
v
v
v
v
v
v
Tables 2–5
2K × 2
v
v
v
v
v
v
v
v
v
v
v
and
1K × 4
v
v
v
v
v
2–6
v
v
v
v
v
v
Write Port
summarize the possible M4K RAM block
512 × 8
Port B
v
v
v
v
v
128 × 32 512 × 9 256 × 18
v
v
v
v
v
v
Stratix Device Handbook, Volume 1
256 × 16
v
v
v
v
v
v
v
v
512 × 9
Stratix Architecture
v
v
v
v
v
256 × 18
128 × 36
v
v
v
v
v
2–31
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