EP1S10F484C7N Altera, EP1S10F484C7N Datasheet - Page 187
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484C7N
Manufacturer Part Number
EP1S10F484C7N
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F484C7N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
10570
Family Type
Stratix
No. Of I/o's
335
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
420MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484C7N
Manufacturer:
ALTERA
Quantity:
455
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Power
Consumption
Altera Corporation
January 2006
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
C
C
C
C
C
Table 4–33. Stratix Device Capacitance
IOTB
IOLR
CLKTB
CLKLR
CLKLR+
Symbol
When tx_outclock port of altlvds_tx megafunction is 717 MHz, V
Pin pull-up resistance values will lower if an external source drives the pin higher than V
Drive strength is programmable according to the values shown in the Stratix Architecture chapter of the Stratix
Device Handbook, Volume 1.
V
Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within ±0.5 pF.
V
REF
IO
and V
Tables 4–10
specifies the center point of the switching range.
CM
Input capacitance on I/O pins in I/O banks
3, 4, 7, and 8.
Input capacitance on I/O pins in I/O banks
1, 2, 5, and 6, including high-speed
differential receiver and transmitter pins.
Input capacitance on top/bottom clock input
pins:
Input capacitance on left/right clock inputs:
CLK1
Input capacitance on left/right clock inputs:
CLK0
have multiple ranges and values for J=1 through 10.
CLK[4:7]
,
,
through 4–33:
CLK3
CLK2
,
,
CLK8
CLK9
Altera
power calculator and the PowerGauge
software.
The interactive power calculator on the Altera web site is typically used
prior to designing the FPGA in order to get a magnitude estimate of the
device power. The Quartus II software PowerGauge feature allows you to
apply test vectors against your design for more accurate power
consumption modeling.
In both cases, these calculations should only be used as an estimation of
power, not as a specification.
Stratix devices require a certain amount of power-up current to
successfully power up because of the small process geometry on which
they are fabricated.
Table 4–34
power a Stratix device. This specification is for commercial operating
conditions. Measurements were performed with an isolated Stratix
device on the board to characterize the power-up current of an isolated
Parameter
and
,
, and
CLK10
CLK[12:15]
®
offers two ways to calculate power for a design: the Altera web
CLK11
Note (5)
shows the maximum power-up current (I
.
.
.
Minimum
O D ( m i n )
TM
Stratix Device Handbook, Volume 1
feature in the Quartus
Typical
DC & Switching Characteristics
11.5
11.5
8.2
7.8
4.4
= 235 mV on the output clock pin.
CCIO
CCINT
Maximum
.
) required to
®
II
Unit
pF
pF
pF
pF
pF
4–17
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