EP1S10F484C7N Altera, EP1S10F484C7N Datasheet - Page 12
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484C7N
Manufacturer Part Number
EP1S10F484C7N
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F484C7N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
10570
Family Type
Stratix
No. Of I/o's
335
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
420MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484C7N
Manufacturer:
ALTERA
Quantity:
455
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Features
1–4
Stratix Device Handbook, Volume 1
Note to
(1)
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
Pitch (mm)
Area (mm
Length × width (mm × mm)
Table 1–3. Stratix Package Options & I/O Pin Counts
Table 1–4. Stratix BGA Package Sizes
Device
All I/O pin counts include 20 dedicated clock input pins (clk[15..0]p, clk0n, clk2n, clk9n, and clk11n)
that can be used for data inputs.
Table
2
)
Dimension
1–3:
672-Pin
BGA
345
426
473
956-Pin
Stratix devices are available in space-saving FineLine BGA
array (BGA) packages (see
support vertical migration within the same package (for example, you
can migrate between the EP1S10, EP1S20, and EP1S25 devices in the 672-
pin BGA package). Vertical migration means that you can migrate to
devices whose dedicated pins, configuration pins, and power pins are the
same for a given package across device densities. For I/O pin migration
across densities, you must cross-reference the available I/O pins using
the device pin-outs for all planned densities of a given package type to
identify which I/O pins are migrational. The Quartus
automatically cross reference and place all pins except differential pins
for migration when given a device migration list. You must use the pin-
outs for each device to verify the differential placement migration. A
future version of the Quartus II software will support differential pin
migration.
BGA
683
683
683
683
FineLine
484-Pin
BGA
335
361
672 Pin
35 × 35
1,225
1.27
FineLine
672-Pin
BGA
345
426
473
Tables 1–3
FineLine
780-Pin
BGA
426
586
597
597
615
through 1–5). All Stratix devices
1,020-Pin
FineLine
BGA
706
726
773
773
773
956 Pin
40 × 40
®
1,600
1.27
Altera Corporation
II software can
®
and ball-grid
1,508-Pin
FineLine
1,022
1,203
BGA
July 2005
822
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