EP1S10F484C7N Altera, EP1S10F484C7N Datasheet - Page 35

• Manufacturer Part Number: EP1S10F484C7N
• Description: IC STRATIX FPGA 10K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F484C7N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 335
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 335
• Frequency (max): 420.17MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 10570
• Family Type: Stratix
• No. Of I/o's: 335
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.6V
• Operating Frequency Max: 420MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

TriMatrix
Memory
Altera Corporation
July 2005
TriMatrix memory consists of three types of RAM blocks: M512, M4K,
and M-RAM blocks. Although these memory blocks are different, they
can all implement various types of memory with or without parity,
including true dual-port, simple dual-port, and single-port RAM, ROM,
and FIFO buffers.
RAM blocks.
Maximum
performance
True dual-port
memory
Simple dual-port
memory
Single-port memory
Shift register
ROM
FIFO buffer
Byte enable
Parity bits
Mixed clock mode
Memory initialization
Simple dual-port
memory mixed width
support
True dual-port
memory mixed width
support
Power-up conditions
Register clears
Mixed-port read-
during-write
Table 2–3. TriMatrix Memory Features (Part 1 of 2)
Memory Feature
Table 2–3
Outputs cleared
Input and output
registers
Unknown
output/old data
M512 RAM Block
(32 × 18 Bits)
shows the size and features of the different
v
v
v
v
v
v
v
v
v
(1)
Stratix Device Handbook, Volume 1
Outputs cleared
Input and output
registers
Unknown
output/old data
M4K RAM Block
(128 × 36 Bits)
(1)
v
v
v
v
v
v
v
v
v
v
v
v
Stratix Architecture
unknown
Output registers
Unknown output
Outputs
(4K × 144 Bits)
M-RAM Block
(1)
v
v
v
(2)
v
v
v
v
v
v
2–21