EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 100

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–38
Cyclone IV Device Handbook, Volume 1
The rselodd bit indicates an odd divide factor for the VCO output frequency with a
50% duty cycle. For example, if the post-scale divide factor is three, the high and low
time count values are 2 and 1, respectively, to achieve this division. This implies a
67%–33% duty cycle. If you need a 50%–50% duty cycle, you must set the rselodd
control bit to 1 to achieve this duty cycle despite an odd division factor. The PLL
implements this duty cycle by transitioning the output clock from high-to-low on a
falling edge of the VCO output clock. When you set rselodd = 1, subtract 0.5 cycles
from the high time and add 0.5 cycles to the low time.
For example:
■
■
■
Scan Chain Description
Cyclone IV PLLs have a 144-bit scan chain.
Table 5–7
Table 5–7. Cyclone IV PLL Reprogramming Bits
C4
C3
C2
C1
C0
M
N
Charge Pump
Loop Filter
Total number of bits:
Notes to
(1) LSB bit for C4 low
(2) These two control bits include rbypass, for bypassing the counter, and rselodd, to select the output clock
(3) MSB bit for loop filter is the last bit shifted into the scan chain.
High time count = 2 cycles
Low time count = 1 cycle
rselodd = 1 effectively equals:
■
■
■
(1)
Block Name
duty cycle.
High time count = 1.5 cycles
Low time count = 1.5 cycles
Duty cycle = (1.5/3)% high time count and (1.5/3)% low time count
Table
lists the number of bits for each component of the PLL.
(3)
5–7:
-
count value is the first bit shifted into the scan chain.
Counter
16
16
16
16
16
16
16
9
9
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Number of Bits
Other
2
2
2
2
2
2
2
(2)
(2)
(2)
(2)
(2)
(2)
(2)
0
0
© December 2010 Altera Corporation
PLL Reconfiguration
Total
144
18
18
18
18
18
18
18
9
9