EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 284

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–4
Transmitter Channel Datapath
TX Phase Compensation FIFO
Byte Serializer
Cyclone IV Device Handbook, Volume 2
f
1
The transceiver channel interfaces through the PIPE when configured for PCIe
protocol implementation. The PIPE is compliant with version 2.00 of the
for the PCI Express Architecture
The following sections describe the Cyclone IV GX transmitter channel datapath
architecture as shown in
The TX phase compensation FIFO compensates for the phase difference between the
low-speed parallel clock and the FPGA fabric interface clock, when interfacing the
transmitter channel to the FPGA fabric (directly or through the PIPE and
PCIe hard IP). The FIFO is four words deep, with latency between two to three
parallel clock cycles.
diagram.
Figure 1–4. TX Phase Compensation FIFO Block Diagram
Note to
(1) The x refers to the supported 8-, 10-, 16-, or 20-bits transceiver channel width.
The FIFO can operate in registered mode, contributing to only one parallel clock cycle
of latency in Deterministic Latency functional mode. For more information, refer to
“Deterministic Latency Mode” on page
For more information about FIFO clocking, refer to
Interface Clocking” on page
The byte serializer divides the input datapath width by two to allow transmitter
channel operation at higher data rates while meeting the maximum FPGA fabric
frequency limit. This module is required in configurations that exceed the maximum
FPGA fabric-transceiver interface clock frequency limit and optional in configurations
that do not.
■
■
■
■
■
Figure
TX Phase Compensation FIFO
Byte Serializer
8B/10B Encoder
Serializer
Transmitter Output Buffer
tx_datain[x..0] (1)
1–4:
Figure 1–4
Figure
1–39.
specification.
1–3:
shows the TX phase compensation FIFO block
wr_clk
Compensation
TX Phase
1–68.
FIFO
rd_clk
Chapter 1: Cyclone IV Transceivers Architecture
“FPGA Fabric-Transceiver
or the 8B/10B encoder
tx_phase_comp_fifo_error
the byte serializer
© December 2010 Altera Corporation
Data output to
Transmitter Channel Datapath
PHY Interface