EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 334

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–54
GIGE Mode
Cyclone IV Device Handbook, Volume 2
1
Figure 1–53. Compliance Pattern Transmission Support in PCI Express (PIPE) Mode
Reset Requirement
Cyclone IV GX devices meets the PCIe reset time requirement from device power up
to the link active state with the configuration schemes listed in
Table 1–18. Electrical Idle Inference Conditions
GIGE mode provides the transceiver channel datapath configuration for GbE
(specifically the 1000 Base-X physical layer device (PHY) standard) protocol
implementation. The Cyclone IV GX transceiver provides the PMA and the following
PCS functions as defined in the IEEE 802.3 specification for 1000 Base-X PHY:
■
■
■
Cyclone IV GX transceivers do not have built-in support for some PCS functions such
as auto-negotiation state machine, collision-detect, and carrier-sense. If required, you
must implement these functions in a user logic or external circuits.
Note to
(1) EP4CGX30 device in F484 package fulfills the PCIe reset time requirement using FPP configuration scheme with
8B/10B encoding and decoding
synchronization
upstream transmitter and local receiver clock frequency compensation (rate
matching)
configuration time of 41 ms.
EP4CGX30
EP4CGX110
EP4CGX150
EP4CGX15
EP4CGX22
EP4CGX50
EP4CGX75
Table
Device
tx_forcedispcompliance
1–18:
tx_ctrldetect[1..0]
(1)
tx_datain[15..0]
Fast passive parallel (FPP)
Configuration Scheme
Passive serial (PS)
/K28.5/D21.5/
B5BC
FPP
FPP
FPP
PS
PS
/K28.5/D10.2/
4ABC
Chapter 1: Cyclone IV Transceivers Architecture
01
/K28.5/D21.5/
B5BC
Configuration Time (ms)
© December 2010 Altera Corporation
Table
/K28.5/D10.2/
Transceiver Functional Modes
51
92
92
41
41
70
70
4ABC
1–17.