EP1AGX90EF1152C6 Altera, EP1AGX90EF1152C6 Datasheet - Page 23

• Manufacturer Part Number: EP1AGX90EF1152C6
• Description: IC ARRIA GX FPGA 90K 1152FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX90EF1152C6

• Number Of Logic Elements/cells: 90220
• Number Of Labs/clbs: 4511
• Total Ram Bits: 4477824
• Number Of I /o: 538
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 2: Arria GX Architecture
Transceivers
Figure 2–16. Before and After the Channel Aligner
© December 2009 Altera Corporation
Figure 2–16
channels after the channel aligner.
Rate Matcher
In asynchronous systems, the upstream transmitter and local receiver can be clocked
with independent reference clock sources. Frequency differences in the order of a few
hundred PPM can potentially corrupt the data at the receiver.
The rate matcher compensates for small clock frequency differences between the
upstream transmitter and the local receiver clocks by inserting or removing skip
characters from the inter packet gap (IPG) or idle streams. It inserts a skip character if
the local receiver is running a faster clock than the upstream transmitter. It deletes a
skip character if the local receiver is running a slower clock than the upstream
transmitter. The Quartus II software automatically configures the appropriate skip
character as specified in the IEEE 802.3 for GIGE mode and PCI-Express Base
Specification for PCI Express (PIPE) mode. The rate matcher is bypassed in Serial
RapidIO and must be implemented in the PLD logic array or external circuits
depending on your system design.
Table 2–5
XAUI, PCI Express (PIPE), GIGE, and Basic functional modes.
Table 2–5. Rate Matcher PPM Tolerance
Lane 3
Lane 3
Lane 2
Lane 1
Lane 0
PCI Express (PIPE)
Function Mode
lists the maximum frequency difference that the rate matcher can tolerate in
Lane 1
shows misaligned channels before the channel aligner and the aligned
Lane 0
Basic
XAUI
GIGE
Lane 2
K
K
K
K
K
K
K
K
K
K
K
K
K
K
R
R
R
R
R
K
R
K
A
A
A
A
A
R
A
R
K
K
K
K
K
A
K
A
R
R
R
R
R
K
R
K
R
R
R
R
R
R
R
R
K
K
K
K
K
R
K
R
± 100
± 300
± 100
± 300
K
K
K
K
K
PPM
K
K
K
R
R
R
R
R
K
R
K
K
K
K
K
K
R
Arria GX Device Handbook, Volume 1
K
R
R
R
R
R
R
K
R
K
R
R
2–17