EP1AGX90EF1152C6 Altera, EP1AGX90EF1152C6 Datasheet - Page 31

• Manufacturer Part Number: EP1AGX90EF1152C6
• Description: IC ARRIA GX FPGA 90K 1152FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX90EF1152C6

• Number Of Logic Elements/cells: 90220
• Number Of Labs/clbs: 4511
• Total Ram Bits: 4477824
• Number Of I /o: 538
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 2: Arria GX Architecture
Transceivers
Figure 2–22. Input Reference Clock Sources
© December 2009 Altera Corporation
Inter-Transceiver Lines [2]
Inter-Transceiver Lines [1]
Inter-Transceiver Lines [0]
The transmitter PLL multiplies the input reference clock to generate a high-speed
serial clock at a frequency that is half the data rate of the configured functional mode.
This high-speed serial clock (or its divide-by-two version if the functional mode uses
byte serializer) is fed to the CMU clock divider block. Depending on the configured
functional mode, the CMU clock divider block divides the high-speed serial clock to
generate the low-speed parallel clock that clocks the transceiver PCS logic in the
associated channel. The low-speed parallel clock is also forwarded to the PLD logic
array on the tx_clkout or coreclkout ports.
The receiver PLL in each channel is also fed by an input reference clock. The receiver
PLL along with the clock recovery unit generates a high-speed serial recovered clock
and a low-speed parallel recovered clock. The low-speed parallel recovered clock
feeds the receiver PCS logic until the rate matcher. The CMU low-speed parallel clock
clocks the rest of the logic from the rate matcher until the receiver phase
compensation FIFO. In modes that do not use a rate matcher, the receiver PCS logic is
clocked by the recovered clock until the receiver phase compensation FIFO.
The input reference clock to the transmitter and receiver PLLs can be derived from:
■
■
■
Figure 2–22
PLL.
One of two available dedicated reference clock input pins (REFCLK0 or REFCLK1)
of the associated transceiver block
PLD clock network (must be driven directly from an input clock pin and cannot be
driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of other
transceiver blocks
Dedicated
REFCLK0
Dedicated
REFCLK1
Inter-Transceiver Lines [2:0]
shows the input reference clock sources for the transmitter and receiver
Global Clock (1)
Global Clock (1)
/2
/2
Transceiver Block 0
Transmitter
Receiver
PLL
PLLs
Transceiver Block 1
Four
Transceiver Block 2
Arria GX Device Handbook, Volume 1
2–25