EP2SGX90FF1508C3N Altera, EP2SGX90FF1508C3N Datasheet - Page 155

IC STRATIX II GX 90K 1508-FBGA

EP2SGX90FF1508C3N

Manufacturer Part Number
EP2SGX90FF1508C3N
Description
IC STRATIX II GX 90K 1508-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX90FF1508C3N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
650
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1508-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1772
EP2SGX90FF40C3N
EP2SGX90FF40C3NES

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX90FF1508C3N
Manufacturer:
ALTERA30
Quantity:
121
Part Number:
EP2SGX90FF1508C3N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX90FF1508C3N
Manufacturer:
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0
Altera Corporation
October 2007
Previous Chapter
02 changes:
June 2006, v1.2
Previous Chapter
02 changes:
April 2006, v1.1
Previous Chapter
02 changes:
October 2005
v1.0
Previous Chapter
03 changes:
August 2006, v1.4
Previous Chapter
03 changes:
June 2006, v1.3
Previous Chapter
03 changes:
April 2006, v1.2
Table 2–42. Document Revision History (Part 5 of 6)
Document
Date and
Version
Added chapter to the Stratix II GX Device
Handbook.
Updated notes 1 and 2 in Figure 2–1.
Updated “Byte Serializer” section.
Updated Tables 2–4, 2–7, and 2–16.
Updated “Programmable Output Driver”
section.
Updated Figure 2–12.
Updated “Programmable Pre-Emphasis”
section.
Added Table 2–11.
Added “Dynamic Reconfiguration” section.
Added “Calibration Block” section.
Updated “Programmable Equalizer”
section, including addition of Figure 2–18.
Updated Figure 2–3.
Updated Figure 2–7.
Updated Table 2–4.
Updated “Transmit Buffer” section.
Updated Table 3–18 with note.
Updated note 2 in Figure 3–41.
Updated column title in Table 3–21.
Updated note 1 in Table 3–9.
Updated note 1 in Figure 3–40.
Updated note 2 in Figure 3–41.
Updated Table 3–16.
Updated Figure 3–56.
Updated Tables 3–19 through 3–22.
Updated Tables 3–25 and 3–26.
Updated “Fast PLL & Channel Layout”
section.
Changes Made
Stratix II GX Device Handbook, Volume 1
Updated input frequency range in
Table 2–4.
Updated input frequency range in
Table 2–4.
Added 1,152-pin FineLine BGA package
information for EP2SGX60 device in
Table 3–16.
Summary of Changes
Stratix II GX Architecture
2–147

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