EP2SGX90FF1508C3N Altera, EP2SGX90FF1508C3N Datasheet - Page 84

IC STRATIX II GX 90K 1508-FBGA

EP2SGX90FF1508C3N

Manufacturer Part Number
EP2SGX90FF1508C3N
Description
IC STRATIX II GX 90K 1508-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX90FF1508C3N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
650
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1508-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1772
EP2SGX90FF40C3N
EP2SGX90FF40C3NES

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0
TriMatrix Memory
Figure 2–53. M-RAM Block Control Signals
2–76
Stratix II GX Device Handbook, Volume 1
Dedicated
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
6
clock_a
Similar to all RAM blocks, M-RAM blocks can have different clocks on
their inputs and outputs. Either of the two clocks feeding the block can
clock M-RAM block registers (renwe, address, byte enable, datain,
and output registers). The output register can be bypassed. The six
labclk signals or local interconnect can drive the control signals for the
A and B ports of the M-RAM block. ALMs can also control the clock_a,
clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and
clocken_b signals, as shown in
The R4, R24, C4, and direct link interconnects from adjacent LABs on
either the right or left side drive the M-RAM block local interconnect. Up
to 16 direct link input connections to the M-RAM block are possible from
the left adjacent LABs and another 16 possible from the right adjacent
LAB. M-RAM block outputs can also connect to left and right LABs
through direct link interconnect.
for the EP2SGX130 device and the location of the M-RAM interfaces.
Figures 2–55
the logic array.
clocken_a
aclr_a
and
renwe_a
2–56
show the interface between the M-RAM block and
renwe_b
aclr_b
Figure 2–54
Figure
clocken_b
2–53.
clock_b
shows an example floorplan
Altera Corporation
October 2007
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect

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