EP2SGX90FF1508C3N Altera, EP2SGX90FF1508C3N Datasheet - Page 24

• Manufacturer Part Number: EP2SGX90FF1508C3N
• Description: IC STRATIX II GX 90K 1508-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90FF1508C3N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 650
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1508-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1772; EP2SGX90FF40C3N; EP2SGX90FF40C3NES

Transceivers
2–16
Stratix II GX Device Handbook, Volume 1
Figure 2–13. Programmable Receiver Termination
If a design uses external termination, the receiver must be externally
terminated and biased to 0.85 V or 1.2 V.
of an external termination and biasing circuit.
Figure 2–14. External Termination and Biasing Circuit
Programmable Equalizer
The Stratix II GX receivers provide a programmable receive equalization
feature to compensate the effects of channel attenuation for high-speed
signaling. PCB traces carrying these high-speed signals have low-pass
filter characteristics. The impedance mismatch boundaries can also cause
signal degradation. The equalization in the receiver diminishes the lossy
attenuation effects of the PCB at high frequencies.
50/60/75- Ω
Termination
Resistance
Transmission
Line
50, 60, or 75 Ω
50, 60, or 75 Ω
V
Receiver External Termination
and Biasing
DD
× {R2/(R1 + R 2)} = 0.85/1.2 V
Receiver External Termination
R1/R2 = 1K
V
C1
and Biasing
DD
V
CM
Figure 2–14
R2
R1
Stratix II GX Device
shows an example
Differential
Altera Corporation
Buffer
RXIN
RXIP
Input
Receiver
October 2007