EP2SGX90FF1508C3N Altera, EP2SGX90FF1508C3N Datasheet - Page 6

IC STRATIX II GX 90K 1508-FBGA

EP2SGX90FF1508C3N

Manufacturer Part Number
EP2SGX90FF1508C3N
Description
IC STRATIX II GX 90K 1508-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX90FF1508C3N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
650
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1508-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1772
EP2SGX90FF40C3N
EP2SGX90FF40C3NES

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX90FF1508C3N
Manufacturer:
ALTERA30
Quantity:
121
Part Number:
EP2SGX90FF1508C3N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX90FF1508C3N
Manufacturer:
ALTERA
0
Features
1–4
Stratix II GX Device Handbook, Volume 1
Note to
(1)
Note to
(1)
Package
EP2SGX30C
EP2SGX60C
EP2SGX30D
EP2SGX60D
EP2SGX60E
EP2SGX90E
EP2SGX90F
EP2SGX130G
Table 1–1. Stratix II GX Device Features (Part 2 of 2)
Table 1–2. Stratix II GX Package Options (Pin Counts and Transceiver Channels)
Device
Includes two sets of dual-purpose differential pins that can be used as two additional channels for the differential
receiver or differential clock inputs.
Includes two differential clock inputs that can also be used as two additional channels for the differential receiver.
Feature
Table
Table
1–1:
1–2:
Transceiver
Channels
12
12
16
20
4
4
8
8
EP2SGX30C/D
FineLine BGA
C
780-pin
Stratix II GX devices are available in space-saving FineLine BGA
packages (refer to
migration within the same package. Vertical migration means that you
can migrate to devices whose dedicated pins, configuration pins, and
power pins are the same for a given package across device densities. For
I/O pin migration across densities, you must cross-reference the available
I/O pins using the device pin-outs for all planned densities of a given
package type to identify which I/O pins are migratable.
Stratix II GX device package sizes.
Receive
Source-Synchronous
D
31
31
31
31
42
47
59
73
Channels
FineLine BGA
(1)
C
780-pin
EP2SGX60C/D/E
Transmit
Table
29
29
29
29
42
45
59
71
D
1,152-pin
1–2). All Stratix II GX devices support vertical
FineLine
BGA
FineLine BGA
E
(29 mm)
780-Pin
361
364
361
364
1,152-pin
FineLine
Maximum User I/O Pin Count
BGA
E
EP2SGX90E/F
FineLine BGA
1,152-Pin
(35 mm)
534
558
1,508-pin
FineLine
BGA
F
Altera Corporation
Table 1–3
FineLine BGA
EP2SGX130/G
FineLine BGA
October 2007
1,508-Pin
(40 mm)
1,508-pin
650
734
lists the
G

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