PNX1502E/G,557 NXP Semiconductors, PNX1502E/G,557 Datasheet - Page 315

• Manufacturer Part Number: PNX1502E/G,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1298; 935277748557; PNX1502E/G

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 1:
Figure 2:
DMA
CPU
The two MTL Ports of the DDR SDRAM Controller
Arbitration in the DDR Controller
2.1.3 Observing Start State
2.2.1 The First Level of Arbitration: Between the DMA and the CPU
2.2 Arbitration
Instead the DDR controller, once configured, executes an exit of self-refresh mode
which starts back on the DDR devices. There is no boot scripts provision for this
mode, therefore an external eeprom is required to activate this mode.
The START and WARM_START fields of MMIO register IP_2031_CTL will be set to
‘0’ when the respective start action has completed. Do not perform a start action
while the DDR controller is still busy performing a previous start action.
The DDR SDRAM Controller provides an arbiter between the DMA traffic (generated
by the PNX15xx/952x Series modules) and the TM3260 CPU as pictured in
on page
The DDR SDRAM Controller arbiter is responsible for scheduling between MTL
transaction requests from the different MTL ports. The arbitration scheme has been
optimized to achieve a high DDR bandwidth efficiency (at the cost of DDR latency).
The arbitration flow is pictured in
MTL port 0
MTL port 1
9-315.
CPUs out of budget
do second level
DMA arbitration
in HRT window
Rev. 4.0 — 03 December 2007
begin
OR
end
Figure
arbitration
CPU wins
2.
DDR command
request queue
PNX15xx/952x Series
Chapter 9: DDR Controller
© NXP B.V. 2007. All rights reserved.
Section 1
9-315