ADE7566ASTZF8 Analog Devices Inc, ADE7566ASTZF8 Datasheet - Page 133

• Manufacturer Part Number: ADE7566ASTZF8
• Description: IC ENERGY METER MCU 8K 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7566ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE75xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SERIAL PERIPHERAL INTERFACE (SPI)
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 integrate a complete hardware serial peripheral
interface on-chip. The SPI is full duplex so that eight bits of data
are synchronously transmitted and simultaneously received.
This SPI implementation is double buffered, allowing users to
read the last byte of received data while a new byte is shifted in.
The next byte to be transmitted can be loaded while the current
byte is shifted out.
The SPI port can be configured for master or slave operation.
The physical interface to the SPI is via the MISO (P0.5/MISO),
MOSI (P0.4/MOSI/SDATA), SCLK (P0.6/SCLK/T0), and SS
SPI REGISTERS
Table 145. SPI SFR List
SFR Address
0x9A
0x9B
0xE8
0xE9
0xEA
Table 146. SPI/I
Bit
[7:0]
Table 147. SPI/I
Bit
[7:0]
Mnemonic
SPI2CTx
Mnemonic
SPI2CRx
2
2
C Transmit Buffer SFR (SPI2CTx, Address 0x9A)
C Receive Buffer SFR (SPI2CRx, Address 0x9B)
SPI2CTx
SPI2CRx
SPISTAT
Default
0
Mnemonic
SPIMOD1
SPIMOD2
Default
0
Description
SPI or I
FIFO input. When a write is requested, the FIFO output is sent on the SPI or I
Description
SPI or I
transferred to SPI2CRx SFR. A new data byte from the SPI or I
R/W
W
R
R/W
R/W
R/W
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
2
2
C transmit buffer. When the SPI2CTx SFR is written, its content is transferred to the transmit
C receive buffer. When SPI2CRx SFR is read, one byte from the receive FIFO output is
Length (Bits)
8
8
8
8
8
Rev. B | Page 133 of 152
Default
0
0
0x10
0
0
(P0.7/ SS /T1) pins, while the firmware interface is via the SPI
Configuration SFR 1 (SPIMOD1, Address 0xE8), the SPI
Configuration SFR 2 (SPIMOD2, Address 0xE9), the SPI
interrupt status SFR (SPISTAT, Address 0xEA), the SPI/I
transmit buffer SFR (SPI2CTx, Address 0x9A), and the SPI/I
receive buffer SFR (SPI2CRx, Address 0x9B).
Note that the SPI pins are shared with the I
user can enable only one interface at a time. The SCPS bit in the
configuration SFR (CFG, Address 0xAF) selects which peripheral
is active.
Description
SPI/I
SPI/I
SPI Configuration SFR 1 (see Table 148).
SPI Configuration SFR 2 (see Table 149).
SPI/I
2
2
2
C transmit buffer (see Table 146).
C receive buffer (see Table 147).
C interrupt status (see Table 150).
2
C bus is written to the FIFO input.
2
C bus.
2
C pins. Therefore, the
2
C
2
C